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| Number | Title | Issue Date |
| 8124471 | Method of post-mold grinding a semiconductor package A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generat... | 02/28/2012 |
| 8003459 | Method for forming semiconductor devices with active silicon height variation A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtr... | 08/23/2011 |
| 7998806 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first ... | 08/16/2011 |
| 7820504 | Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of de... | 10/26/2010 |
| RE41538 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the d... | 08/17/2010 |
| 7666735 | Method for forming semiconductor devices with active silicon height variation A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtr... | 02/23/2010 |
| 7524721 | High voltage CMOS device and method of fabricating the same A method of fabricating a high voltage CMOS device is provided that does not require a separate mask for forming a photo align key when forming a high voltage deep well region. The method includes forming a relatively thick first oxide film pattern exposing a predet... | 04/28/2009 |
| 7510927 | LOCOS isolation for fully-depleted SOI devices The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pa... | 03/31/2009 |
| 7432167 | Method of fabricating a strained silicon channel metal oxide semiconductor transistor The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask layer on the gate structure, performing an etching process to form tw... | 10/07/2008 |
| 7425475 | Method for fabricating semiconductor device and semiconductor device A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions ea... | 09/16/2008 |
| 7422960 | Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th... | 09/09/2008 |
| 7381631 | Use of expanding material oxides for nano-fabrication This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjac... | 06/03/2008 |
| 7364963 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal proces... | 04/29/2008 |
| 7347228 | Method of making semiconductor devices A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress ... | 03/25/2008 |
| 7341502 | Methods and systems for planarizing workpieces, e.g., microelectronic workpieces Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a planarizing condition. This process indicator may, for example, change color in response to reaching a particular... | 03/11/2008 |
| 7335549 | Semiconductor device and method for fabricating the same An N-channel transistor includes: an N-type source region, a gate electrode, a P-type body region, an N-type drain offset region, and a drain contact region, which is an N-type drain region. The transistor further includes a gate insulating film that has a thin oxid... | 02/26/2008 |
| 7332387 | MOSFET structure and method of fabricating the same A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced b... | 02/19/2008 |
| 7320908 | Methods of forming semiconductor devices having buried oxide patterns Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor a... | 01/22/2008 |
| 7314792 | Method for fabricating transistor of semiconductor device A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to fo... | 01/01/2008 |
| 7279423 | Forming a copper diffusion barrier Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper l... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7279377 | Method and structure for shallow trench isolation during integrated circuit device manufacture A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into... | 10/09/2007 |
| 7276417 | Hybrid STI stressor with selective re-oxidation anneal A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectr... | 10/02/2007 |
| 7259055 | Method of forming high-luminescence silicon electroluminescence device A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of ... | 08/21/2007 |
| 7253048 | Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit A semiconductor integrated circuit has a CMOS transistor formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Thermal oxidation is conducted to form a LOCOS for element... | 08/07/2007 |
| 7241662 | Reduction of field edge thinning in peripheral devices A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet... | 07/10/2007 |
| 7235460 | Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t... | 06/26/2007 |
| 7235304 | Optical sensor An optical sensor that can receive light ranging from visible light to infrared light is provided. A thin beta-iron disilicide semiconductor film is formed on a silicon substrate. Light in the visible region is received by silicon, and light in the infrared region i... | 06/26/2007 |
| 7202134 | Method of forming transistors with ultra-short gate feature A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set... | 04/10/2007 |
| 7198992 | Method of manufacturing a semiconductor device comprising doping steps using gate electrodes and resists as masks The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semicon... | 04/03/2007 |
| 7192840 | Semiconductor device fabrication method using oxygen ion implantation A method of fabricating a semiconductor device having a silicon layer disposed on an insulating film. Oxygen ions are implanted into selected parts of the silicon layer, which are then oxidized to form isolation regions dividing the silicon layer into a plurality of... | 03/20/2007 |
| 7172914 | Method of making uniform oxide layer A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial lay... | 02/06/2007 |
| 7169670 | Method of forming gate oxide layer in semiconductor device Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substr... | 01/30/2007 |
| 7145187 | Substrate independent multiple input bi-directional ESD protection structure In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polari... | 12/05/2006 |
| 7132656 | High speed and high efficiency Si-based photodetectors using waveguides formed with silicide for near IR applications According to this invention, silicon-based photodetectors using waveguides formed with silicide regions can have high speed and high efficiency for near IR applications. Utilizing the unique properties of silicides, the proposed method provides a simple and elegant ... | 11/07/2006 |
| 7132372 | Method for preparing a semiconductor substrate surface for semiconductor device fabrication A method for preparing a semiconductor substrate surface (28) for semiconductor device fabrication, includes providing a semiconductor substrate (20) having a pure Ge surface layer (28) or a Ge-containing surface layer (12), such as SiGe.... | 11/07/2006 |
| 7117124 | Trouble detection method, trouble detection apparatus, and temperature controller First determination means 16 determines whether a deviation exceeds a threshold value, measurement means 17 measures the period in which the deviation exceeds the threshold value in accordance with the determination result, second determination means d... | 10/03/2006 |
| 7112482 | Method of forming a field effect transistor A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi... | 09/26/2006 |
| 7105895 | Epitaxial SiObarrier/insulation layer A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects... | 09/12/2006 |
| 7105413 | Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substr... | 09/12/2006 |
