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| Number | Title | Issue Date |
| 7943461 | High-voltage semiconductor device and method for manufacturing the same A high-voltage semiconductor device and a method for manufacturing the same are disclosed. The disclosed high-voltage semiconductor device includes a semiconductor substrate, a first N type well in the semiconductor substrate, a first P type well in the first N type... | 05/17/2011 |
| 7696037 | CMOS (complementary metal oxide semiconductor) technology A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the... | 04/13/2010 |
| 7629214 | Method of making a transistor with a sloped drain diffusion layer Disclosed is that in a method of manufacturing a semiconductor device of the present invention, when first and second P type diffusion layers using as a backgate region, these layers are formed in such a way that their impurity concentration peaks are shifted, respe... | 12/08/2009 |
| 7618857 | Method of reducing detrimental STI-induced stress in MOSFET channels A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top sur... | 11/17/2009 |
| 7482219 | Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layer The present invention provides a technique for forming differently stressed contact etch stop layers, wherein sidewall spacers are removed prior to the formation of the contact etch stop layers. During the partial removal of respective contact etch stop layers, a co... | 01/27/2009 |
| 7439140 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 10/21/2008 |
| 7432136 | Transistors with controllable threshold voltages, and various methods of making and operating same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well f... | 10/07/2008 |
| 7413946 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 08/19/2008 |
| 7410855 | Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f... | 08/12/2008 |
| 7384829 | Patterned strained semiconductor substrate and device A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is... | 06/10/2008 |
| 7365010 | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electr... | 04/29/2008 |
| 7366026 | Flash memory device and method for fabricating the same, and programming and erasing method thereof A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an O... | 04/29/2008 |
| 7354818 | Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termin... | 04/08/2008 |
| 7348232 | Highly activated carbon selective epitaxial process for CMOS In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and formin... | 03/25/2008 |
| 7338850 | Method for manufacturing device isolation film of semiconductor device A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to pr... | 03/04/2008 |
| 7339249 | Semiconductor device An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p typ... | 03/04/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7323367 | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described. ... | 01/29/2008 |
| 7314794 | Low-cost high-performance planar back-gate CMOS A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-ga... | 01/01/2008 |
| 7312485 | CMOS fabrication process utilizing special transistor orientation Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the | 12/25/2007 |
| 7303951 | Method of manufacturing a trench isolation region in a semiconductor device A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over... | 12/04/2007 |
| 7303950 | Semiconductor device, method of manufacturing same and method of designing same A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS... | 12/04/2007 |
| 7297584 | Methods of fabricating semiconductor devices having a dual stress liner In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, an... | 11/20/2007 |
| 7294890 | Fully salicided (FUSA) MOSFET structure A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI reg... | 11/13/2007 |
| 7294903 | Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 11/13/2007 |
| 7288445 | Double gated transistor and method of fabrication Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric... | 10/30/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7273776 | Methods of forming a P-well in an integrated circuit device The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped ... | 09/25/2007 |
| 7265012 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 09/04/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7259072 | Shallow low energy ion implantation into pad oxide for improving threshold voltage stability A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ ... | 08/21/2007 |
| 7253047 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 08/07/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7244646 | Pixel design to improve photodiode capacitance and method of forming same A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent pixels and their associated photodiodes is provided. The shared active area region isolates the two adjacen... | 07/17/2007 |
| 7226859 | Method of forming different silicide portions on different silicon-containing regions in a semiconductor device A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a... | 06/05/2007 |
| 7220650 | Sidewall spacer for semiconductor device and fabrication method thereof An offset spacer layer for an LDD ion implantation process is formed by blanket deposition without photolithography and dry etch processes. The offset spacer layer remaining on LDD regions during an ion implantation process prevents a substrate from silicon loss and... | 05/22/2007 |
| 7218347 | Photoelectric conversion element and solid-state image sensing device using the same Upon reading out signals from a plurality of photodiode layers, highly color-separable signals which suffer less color mixture and noise are read out. A photoelectric conversion element which is formed by alternately stacking photoelectric conversion regions of a fi... | 05/15/2007 |
