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| Number | Title | Issue Date |
| 8084319 | Precisely tuning feature sizes on hard masks via plasma treatment Methods are provided for fabricating devices. A first layer is formed. A hardmask on the first layer is formed. Features on the hardmask are patterned. The sizes of features on the hardmask are reduced by applying a plasma treatment process to form reduced size feat... | 12/27/2011 |
| 8080455 | Method for fabricating semiconductor device with increased breakdown voltage A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shi... | 12/20/2011 |
| 8053305 | Method for producing semiconductor device The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after t... | 11/08/2011 |
| 8043909 | Porous semiconductive film and process for its production The present invention provides a porous semiconductive structure, characterized in that the structure has an electrical conductivity of 5·10−8 S·cm−1 to 10 S·cm−1, and an activation energy of the electrical conductivity of 0... | 10/25/2011 |
| 7906389 | Butted source contact and well strap A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation regio... | 03/15/2011 |
| 7713809 | Image sensor for reduced dark current A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n... | 05/11/2010 |
| 7645664 | Layout pattern for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface ... | 01/12/2010 |
| 7575969 | Buried layer and method A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations. ... | 08/18/2009 |
| 7482218 | Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of the substrate. A drain doped to a second conductivity type opposite to... | 01/27/2009 |
| 7419863 | Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone Complementary IGFETs (210W and 220W or 530 and 540) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the body material of that IGFET up to one of it... | 09/02/2008 |
| 7410855 | Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f... | 08/12/2008 |
| 7384829 | Patterned strained semiconductor substrate and device A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is... | 06/10/2008 |
| 7372105 | Semiconductor device with power supply impurity region A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing... | 05/13/2008 |
| 7354818 | Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termin... | 04/08/2008 |
| 7336530 | CMOS pixel with dual gate PMOS A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS t... | 02/26/2008 |
| 7314794 | Low-cost high-performance planar back-gate CMOS A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-ga... | 01/01/2008 |
| 7309636 | High-voltage metal-oxide-semiconductor device and method of manufacturing the same The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassin... | 12/18/2007 |
| 7300834 | Methods of forming wells in semiconductor devices Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed ... | 11/27/2007 |
| 7294522 | CMOS image sensor and method for fabricating the same A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conduc... | 11/13/2007 |
| 7294889 | Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of firs... | 11/13/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7265039 | Method for fabricating semiconductor device with improved refresh time The present invention relates to a method for fabricating a semiconductor device with improved refresh time. The method includes the steps of: forming a plurality of gate lines on a substrate; forming a plurality of cell junctions by ion-implanting a first dopant wi... | 09/04/2007 |
| 7262110 | Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ... | 08/28/2007 |
| 7259053 | Methods for forming a device isolation structure in a semiconductor device Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material... | 08/21/2007 |
| 7259428 | Semiconductor device using SOI structure having a triple-well region A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well regi... | 08/21/2007 |
| 7253047 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 08/07/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7229870 | Methods of fabricating semiconductor devices Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the ... | 06/12/2007 |
| 7229886 | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a drive... | 06/12/2007 |
| 7217627 | Semiconductor devices having diffusion barrier regions and halo implant regions and methods of fabricating the same The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, form... | 05/15/2007 |
| 7211477 | High voltage field effect device and method Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more... | 05/01/2007 |
| 7192816 | Self-aligned body tie for a partially depleted SOI device structure A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned a... | 03/20/2007 |
| 7187056 | Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo... | 03/06/2007 |
| 7183155 | Non-volatile memory device and fabricating method thereof The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two tr... | 02/27/2007 |
| 7166853 | Active method and system of establishing electrical contact A system for electrically contacting a semiconductor wafer during implanting of the wafer includes one or more pairs of closely spaced contacts located adjacent the semiconductor wafer and a driving circuit connected to the contacts to provide a discharge from one c... | 01/23/2007 |
| 7157322 | Semiconductor device and method for manufacturing same A semiconductor device including an NMOSFET which has an n-type source/drain main region containing arsenic and an n-type source/drain buffer region having arsenic and phosphorous of which a concentration is lower than that of the source/drain main region, and the c... | 01/02/2007 |
| 7145187 | Substrate independent multiple input bi-directional ESD protection structure In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polari... | 12/05/2006 |
| 7144775 | Low-voltage single-layer polysilicon eeprom memory cell The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an ... | 12/05/2006 |
| 7112975 | Advanced probe card and method of fabricating same In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of hol... | 09/26/2006 |
| 7109052 | Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice A method for making an integrated circuit may include forming at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may... | 09/19/2006 |
