Class 438/222 - With epitaxial semiconductor layer formation

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making complementary insulated gate field effect
No. of patents: 171
Last issue date: 05/08/2012

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Number	Title	Issue Date
8173502	Formation of active area using semiconductor growth process without STI integration A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., ...	05/08/2012
8053304	Method of forming high-mobility devices including epitaxially growing a semiconductor layer on a dislocation-blocking layer in a recess formed in a semiconductor substrate A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolati...	11/08/2011
8017472	CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed...	09/13/2011
7985642	Formation of active area using semiconductor growth process without STI integration A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., ...	07/26/2011
7947552	Process for the simultaneous deposition of crystalline and amorphous layers with doping One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is f...	05/24/2011
7867841	Methods of forming semiconductor devices with extended active regions A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface...	01/11/2011
7776679	Method for forming silicon wells of different crystallographic orientations A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining ...	08/17/2010
7622344	Method of manufacturing complementary metal oxide semiconductor transistors A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a ...	11/24/2009
7618856	Method for fabricating strained-silicon CMOS transistors A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active r...	11/17/2009
7588980	Methods of controlling morphology during epitaxial layer formation A first aspect of the invention provides a method of selectively forming an epitaxial layer on a substrate. The method includes heating the substrate to a temperature of less than about 800° C. and employing both silane and dichlorosilane as silicon sources during ...	09/15/2009
7566609	Method of manufacturing a semiconductor structure There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate ...	07/28/2009
7557000	Etching method and structure using a hard mask for strained silicon MOS transistors A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric l...	07/07/2009
7432149	CMOS on SOI substrates with hybrid crystal orientations Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming ...	10/07/2008
7432167	Method of fabricating a strained silicon channel metal oxide semiconductor transistor The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask layer on the gate structure, performing an etching process to form tw...	10/07/2008
7402466	Strained silicon CMOS on hybrid crystal orientations Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material,...	07/22/2008
7393751	Semiconductor structure including laminated isolation region A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolat...	07/01/2008
7393762	Charge-free low-temperature method of forming thin film-based nanoscale materials and structures on a substrate A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of at least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and...	07/01/2008
7390710	Protection of tunnel dielectric using epitaxial silicon Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon...	06/24/2008
7390717	Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for...	06/24/2008
7384837	Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forms a second layer of relaxed SiGe...	06/10/2008
7381622	Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer...	06/03/2008
7372613	Method and device for multistate interferometric light modulation A multi-state light modulator comprises a first reflector. A first electrode is positioned at a distance from the first reflector. A second reflector is positioned between the first reflector and the first electrode. The second reflector is movable between an undriv...	05/13/2008
7364975	Semiconductor device fabrication methods Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the ...	04/29/2008
7361528	Germanium infrared sensor for CMOS imagers A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+silicon layer, forming a silicon-g...	04/22/2008
7354826	Method for forming memory array bitlines comprising epitaxially grown silicon and related structure According to one exemplary embodiment, a method of fabricating a bitline in a memory array includes forming a trench in a substrate, where the trench has sidewalls and a bottom surface. The method further includes performing a selective epitaxial process to partiall...	04/08/2008
7351633	Method of fabricating semiconductor device using selective epitaxial growth A method of fabricating a semiconductor device using selective epitaxial growth (SEG) is disclosed. The method comprises; forming a seed window exposing a portion of a substrate through an interlayer insulating layer, growing a single crystal silicon SEG layer in th...	04/01/2008
7349141	Method and post structures for interferometric modulation An interferometric modulator includes a post structure comprising an optical element. In a preferred embodiment, the optical element in the post structure is a reflective element, e.g., a mirror. In another embodiment, the optical element in the post structure is an...	03/25/2008
7348186	Method for improving a semiconductor substrate having SiGe film and semiconductor device manufactured by using this method A method of improving a semiconductor substrate including a SiGe film on a Si or SOI substrate is provided. The method includes determining a relationship between a film condition of the SiGe film and a hydrogen ion implantation condition used in making the SiGe fil...	03/25/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7326636	Method and circuit structure employing a photo-imaged solder mask In one embodiment, a photo-imageable material is deposited on a circuit structure. The photo-imageable material is then exposed to a pattern of radiation, thereby polymerizing portions of the photo-imageable. Un-polymerized portions of the photo-imageable material a...	02/05/2008
7323733	Nonvolatile memory and fabrication method thereof A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode inc...	01/29/2008
7321457	Process and structure for fabrication of MEMS device having isolated edge posts A method of fabricating an array of MEMS devices includes the formation of support structures located at the edge of upper strip electrodes. A support structure is etched to form a pair of individual support structures located at the edges of a pair of adjacent elec...	01/22/2008
7309902	Microelectronic device with anti-stiction coating One embodiment of a microelectronic device includes a movable plate including a lower surface, a bump positioned on the lower surface, and an anti-stiction coating positioned only on the bump. ...	12/18/2007
7300846	Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the s...	11/27/2007
7294903	Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ...	11/13/2007
7294935	Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle...	11/13/2007
7292469	Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to reduce a resistance of the transition metal oxide layer and applying a se...	11/06/2007
7291880	Transistor assembly Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ...	11/06/2007
7286896	Multi-function teach pendant for a semiconductor manufacturing environment Provided are a device and method for a programmable hand-held device for use in a semiconductor manufacturing environment. In one example, the device includes an interface, a processor, an input device, and a memory. The interface may establish a connection between ...	10/23/2007
7279377	Method and structure for shallow trench isolation during integrated circuit device manufacture A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into...	10/09/2007

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Class 438/222 - With epitaxial semiconductor layer formation