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| Number | Title | Issue Date |
| 8187931 | Method for fabricating a semiconductor device with a substrate protrusion A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least a... | 05/29/2012 |
| 8129235 | Method of fabricating two-step self-aligned contact A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielec... | 03/06/2012 |
| 8105894 | Semiconductor device manufacturing method and semiconductor device A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a g... | 01/31/2012 |
| 8105893 | Diffusion sidewall for a semiconductor structure A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner alo... | 01/31/2012 |
| 8097503 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first... | 01/17/2012 |
| 8067282 | Method for selective formation of trench A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first semiconductor element has a dopant. Second, a wet etching procedure is carri... | 11/29/2011 |
| 8039339 | Separate layer formation in a semiconductor device A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the s... | 10/18/2011 |
| 8039340 | Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum wid... | 10/18/2011 |
| 8021943 | Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surf... | 09/20/2011 |
| 8017471 | Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; formin... | 09/13/2011 |
| 8003458 | Methods of manufacturing a semiconductor device with active regions of different heights Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is e... | 08/23/2011 |
| 7972921 | Integrated circuit isolation system A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, growing the substrate to surround the base insulator region, and... | 07/05/2011 |
| 7939403 | Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed t... | 05/10/2011 |
| 7888197 | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX... | 02/15/2011 |
| 7883956 | Method of forming coplanar active and isolation regions and structures thereof Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bondi... | 02/08/2011 |
| 7858467 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first... | 12/28/2010 |
| 7851298 | Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that e... | 12/14/2010 |
| 7829408 | Laterally double-diffused metal oxide semiconductor transistor and method for fabricating the same The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conducti... | 11/09/2010 |
| 7767515 | Managing integrated circuit stress using stress adjustment trenches Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stre... | 08/03/2010 |
| 7754561 | Method for fabricating isolation film in semiconductor device A method for forming an isolation layer in a semiconductor device comprises forming a trench inside a semiconductor substrate, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench, etching overhangs on ... | 07/13/2010 |
| 7749833 | Semiconductor MOS transistor device and method for making the same A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and ... | 07/06/2010 |
| 7723177 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device that may include steps of forming a pad oxide layer and an insulating layer on a semiconductor substrate; and then performing a first etching process on the semiconductor device to form an insulating layer pattern exp... | 05/25/2010 |
| 7723178 | Shallow and deep trench isolation structures in semiconductor integrated circuits A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor... | 05/25/2010 |
| 7678641 | Semiconductor device and fabrication process thereof There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a d... | 03/16/2010 |
| 7670895 | Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced... | 03/02/2010 |
| 7550343 | Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes In one embodiment, a semiconductor structure used in manufacturing a semiconductor device includes a substrate layer. The structure also includes first and second isolation regions formed by etching an oxide layer provided on the substrate layer to define an epitaxi... | 06/23/2009 |
| 7544560 | Image sensor and fabrication method thereof Example embodiments relate to an image sensor and a fabrication method thereof, capable of reducing dark current and a fabrication method thereof. The image sensor may include a semiconductor substrate including an active region defined by an isolation layer, a phot... | 06/09/2009 |
| 7528031 | Semiconductor device and method for manufacturing the same After formation of a gate insulating film for a high voltage transistor on the entire surface, when removing the gate insulating film existing within a low voltage region, etching is not finished upon expose of an active region, but over etching is performed until t... | 05/05/2009 |
| 7510926 | Technique for providing stress sources in MOS transistors in close proximity to a channel region A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced ef... | 03/31/2009 |
| 7465623 | Methods for fabricating a semiconductor device on an SOI substrate Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region ex... | 12/16/2008 |
| 7439131 | Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r... | 10/21/2008 |
| 7432148 | Shallow trench isolation by atomic-level silicon reconstruction Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidew... | 10/07/2008 |
| 7432149 | CMOS on SOI substrates with hybrid crystal orientations Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming ... | 10/07/2008 |
| 7422960 | Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th... | 09/09/2008 |
| 7419866 | Process of forming an electronic device including a semiconductor island over an insulating layer A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first... | 09/02/2008 |
| 7410858 | Isolation structure configurations for modifying stresses in semiconductor devices An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention i... | 08/12/2008 |
| 7402473 | Semiconductor device and process for producing the same A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around th... | 07/22/2008 |
| 7402494 | Method for fabricating high voltage semiconductor device A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on th... | 07/22/2008 |
| 7396737 | Method of forming shallow trench isolation A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includ... | 07/08/2008 |
| 7390710 | Protection of tunnel dielectric using epitaxial silicon Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon... | 06/24/2008 |
