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| Number | Title | Issue Date |
| 8097502 | Semiconductor light emitting device and method of manufacturing the same Provided is a semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes a substrate, at least two light emitting cells located on the substrate and formed by stacking s... | 01/17/2012 |
| 8053303 | SOI body contact using E-DRAM technology A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within... | 11/08/2011 |
| 8039338 | Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced. ... | 10/18/2011 |
| 7858466 | Different-voltage device manufactured by a CMOS compatible process and high-voltage device used in the different-voltage device A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in hi... | 12/28/2010 |
| 7422938 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 09/09/2008 |
| 7407851 | DMOS device with sealed channel processing A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A fi... | 08/05/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7241668 | Planar magnetic tunnel junction substrate having recessed alignment marks A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment reces... | 07/10/2007 |
| 7226872 | Lightly doped drain MOS transistor A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack including one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partiall... | 06/05/2007 |
| 7186631 | Method for manufacturing a semiconductor device Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon;... | 03/06/2007 |
| 7187000 | High performance tunneling-biased MOSFET and a process for its manufacture A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at ... | 03/06/2007 |
| 7183221 | Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition... | 02/27/2007 |
| 7183573 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of ... | 02/27/2007 |
| 7129533 | High concentration indium fluorine retrograde wells A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3. ... | 10/31/2006 |
| 7052939 | Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-ci... | 05/30/2006 |
| 7026229 | Athermal annealing with rapid thermal annealing system and method A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to ... | 04/11/2006 |
| 7009404 | Method and device for testing the ESD resistance of a semiconductor component To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct current characteristic of the semiconductor component is monitored and the ESD resistance of the respective se... | 03/07/2006 |
| 7002229 | Self aligned Hall with field plate A self aligned Hall sensor system and method are disclosed. A substrate can be provided. A Hall element and a plurality of contacts can then be formed upon the substrate wherein contacts are located in reference to one another. A field plate formed from polysilicon ... | 02/21/2006 |
| 6989309 | High voltage MOS transistor with up-retro well by providing dopant in an epitaxial layer A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The... | 01/24/2006 |
| 6972265 | Metal etch process selective to metallic insulating materials A method is provided which includes patterning one or more metal layers arranged above a metal insulating layer and terminating the patterning process upon exposure of the metal insulating layer. In particular, the method may be adapted to be more selective to the m... | 12/06/2005 |
| 6946376 | Symmetric device with contacts self aligned to gate A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a... | 09/20/2005 |
| 6943072 | Adjustable threshold isolation transistor An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isola... | 09/13/2005 |
| 6940137 | Semiconductor device having an angled compensation implant and method of manufacture therefor The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of ... | 09/06/2005 |
| 6927114 | Method for fabricating a high voltage dual gate device A method for fabricating a high voltage dual gate device is disclosed which limits damage to a device isolation layer by forming a high voltage oxide film after formation of a buffer nitride film. The method includes forming high voltage n-type and p-type well regio... | 08/09/2005 |
| 6913973 | Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single g... | 07/05/2005 |
| 6887750 | Method for manufacturing semiconductor device including implanting a first impurity through an anti-oxidation mask A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages provided in a common substrate. The method includes: (a) introducing a first impurity of a... | 05/03/2005 |
| 6878568 | CMOS imager and method of formation A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface le... | 04/12/2005 |
| 6878595 | Technique for suppression of latchup in integrated circuits (ICS) The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing... | 04/12/2005 |
| 6781206 | Semiconductor device with structure restricting flow of unnecessary current therein Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P− substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-... | 08/24/2004 |
| 6780700 | Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator... | 08/24/2004 |
| 6589834 | Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated f... | 07/08/2003 |
| 6589835 | Method of manufacturing flash memory A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD ... | 07/08/2003 |
| 6582997 | ESD protection scheme for outputs with resistor loading Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal c... | 06/24/2003 |
| 6552256 | Two-stage three-terminal thermionic/thermoelectric coolers A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device.... | 04/22/2003 |
| 6541325 | Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so t... | 04/01/2003 |
| 6492710 | Substrate isolated transistor A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposit... | 12/10/2002 |
| 6475852 | Method of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/05/2002 |
| 6472260 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 10/29/2002 |
| 6472241 | Radical cell device and method for manufacturing groups II-VI compound semiconductor device The closing plates (61b), (61c) are provided on the both end portions of the cylindrical insulator body (61a), the gas introduction tube for introducing a gaseous substance is inserted into one plate (61b) of the closing plates of the plasma chamber (61) ... | 10/29/2002 |
| 6344382 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 02/05/2002 |
