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| Number | Title | Issue Date |
| 8173501 | Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topogra... | 05/08/2012 |
| 8084317 | Semiconductor device and method of manufacturing the same Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spac... | 12/27/2011 |
| 8084318 | Methods of fabricating integrated circuit devices including strained channel regions and related devices A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite side... | 12/27/2011 |
| 8067281 | Method of fabricating complementary metal-oxide-semiconductor (CMOS) Device A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectiv... | 11/29/2011 |
| 7998805 | Component with sensitive component structures and method for the production thereof An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical arcing and galvanically separated from one another. To prevent an arcing b... | 08/16/2011 |
| 7947551 | Method of forming a shallow trench isolation structure An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bot... | 05/24/2011 |
| 7947550 | Method of forming semiconductor device A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that def... | 05/24/2011 |
| 7932143 | Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and... | 04/26/2011 |
| 7883955 | Gate dielectric/isolation structure formation in high/low voltage regions of semiconductor device A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolat... | 02/08/2011 |
| 7875514 | Technique for compensating for a difference in deposition behavior in an interlayer dielectric material By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffe... | 01/25/2011 |
| 7851297 | Dual workfunction semiconductor device A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the meth... | 12/14/2010 |
| 7824977 | Completely decoupled high voltage and low voltage transistor manufacturing processes A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off... | 11/02/2010 |
| 7811878 | Method of manufacturing SOI substrate To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 o... | 10/12/2010 |
| 7785956 | Technique for compensating for a difference in deposition behavior in an interlayer dielectric material By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffe... | 08/31/2010 |
| 7723176 | Method for manufacturing semiconductor device Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics ... | 05/25/2010 |
| 7723175 | Method for manufacturing CMOS circuits A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer ove... | 05/25/2010 |
| 7553721 | Flash memory devices and methods of fabricating the same Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed ... | 06/30/2009 |
| 7537989 | Method for manufacturing SOI substrate To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 o... | 05/26/2009 |
| 7514312 | Method of manufacturing semiconductor device Disclosed herein is a method of manufacturing semiconductor devices. After first isolation trenches are formed in a cell region, second isolation trenches are formed in a peripheral region by an etch process using a photoresist as a mask. As such, top corner portion... | 04/07/2009 |
| 7514313 | Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layer A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further incl... | 04/07/2009 |
| 7442601 | Stress enhanced CMOS circuits and methods for their fabrication A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS tr... | 10/28/2008 |
| 7442630 | Method for fabricating forward and reverse blocking devices A power device includes a gate electrode, a source electrode, and a drain electrode provided within an active region of a semiconductor substrate of first conductivity type. A vertical diffusion region of second conductivity is provided at a periphery the active reg... | 10/28/2008 |
| 7439122 | Method of manufacturing semiconductor device having improved RESURF Trench isolation and method of evaluating manufacturing method A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− | 10/21/2008 |
| 7439131 | Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r... | 10/21/2008 |
| 7432148 | Shallow trench isolation by atomic-level silicon reconstruction Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidew... | 10/07/2008 |
| 7419864 | Semiconductor device and method of manufacturing the same A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a... | 09/02/2008 |
| 7396715 | Semiconductor device and manufacturing method of the same Patterning is performed in such a manner that an end portion fabricated of a second gate insulating film partially overlaps an end portion fabricated of a first gate insulating film. Then, a surface recovery treatment is performed in the aforementioned state where t... | 07/08/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7390710 | Protection of tunnel dielectric using epitaxial silicon Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon... | 06/24/2008 |
| 7381609 | Method and structure for controlling stress in a transistor channel A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adju... | 06/03/2008 |
| 7371632 | Semiconductor device having high-voltage transistor and PIP capacitor and method for fabricating the same A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. ... | 05/13/2008 |
| 7364807 | Thermal barrier coating/environmental barrier coating system for a ceramic-matrix composite (CMC) article to improve high temperature capability In accordance with an embodiment of the invention, an article is provided. The article comprises a substrate comprised of silicon containing material, an environmental barrier coating (EBC) overlying the substrate and a thermal barrier coating (TBC) on the environme... | 04/29/2008 |
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat... | 04/29/2008 |
| 7364963 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal proces... | 04/29/2008 |
| 7364962 | Shallow trench isolation process utilizing differential liners A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce... | 04/29/2008 |
| 7361540 | Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone... | 04/22/2008 |
| 7355265 | Semiconductor integrated circuit A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer for... | 04/08/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7341904 | Capacitorless 1-transistor DRAM cell and fabrication method A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor ma... | 03/11/2008 |
| 7329926 | Semiconductor device with constricted current passage A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the sour... | 02/12/2008 |
