Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 8067280 | High performance CMOS devices and methods for making same An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate ... | 11/29/2011 |
| 7968400 | Short channel LV, MV, and HV CMOS devices Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of th... | 06/28/2011 |
| 7955923 | I/O ESD protection device for high performance circuits A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transist... | 06/07/2011 |
| 7879669 | Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switchin... | 02/01/2011 |
| 7867839 | Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes th... | 01/11/2011 |
| 7867840 | Semiconductor device and method of fabricating the same In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an imp... | 01/11/2011 |
| 7816201 | Semiconductor device and method of manufacturing the same A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region o... | 10/19/2010 |
| 7811877 | Method of controlling metal silicide formation Methods of processing silicon substrates to form metal silicide layers thereover having more uniform thicknesses are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate having a plurality of exposed regions compris... | 10/12/2010 |
| 7772063 | Reduced-step CMOS processes for low-cost radio frequency identification devices Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the num... | 08/10/2010 |
| 7767514 | Methods of implanting dopant into channel regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 08/03/2010 |
| 7727833 | Work function based voltage reference A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold vol... | 06/01/2010 |
| 7704822 | Semiconductor device Embodiments relate to a semiconductor device. According to embodiments, a semiconductor device may include a plurality of wells formed on a substrate, threshold voltage control ion layers formed around surfaces of the wells, device isolation layers arranged between ... | 04/27/2010 |
| 7700429 | Method for forming fin transistor A method for forming a fin transistor includes forming a fin active region, depositing a thin layer doped with impurities over a semiconductor substrate, and forming a channel by diffusing the impurities into the fin active region of the fin transistor. In detail of... | 04/20/2010 |
| 7678640 | Method of threshold voltage control in metal-oxide-semiconductor devices Methods are provided for manufacturing a semiconductor circuit on a substrate of a first conductivity type to control threshold voltages of devices in the circuit. One method involves: (i) forming a photoresist mask on a surface of the substrate defining a well boun... | 03/16/2010 |
| 7674670 | Methods of forming threshold voltage implant regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 03/09/2010 |
| 7645662 | Transistor providing different threshold voltages and method of fabrication thereof A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of t... | 01/12/2010 |
| 7632732 | Method of manufacturing MOS transistor A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to form a second well; removing the first mask pattern; forming a secon... | 12/15/2009 |
| 7569449 | Processes providing high and low threshold p-type and n-type transistors Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first... | 08/04/2009 |
| 7521311 | Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrat... | 04/21/2009 |
| 7442600 | Methods of forming threshold voltage implant regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertain... | 10/28/2008 |
| 7432141 | Large-grain p-doped polysilicon films for use in thin film transistors A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low t... | 10/07/2008 |
| 7413946 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 08/19/2008 |
| 7407850 | N+ poly on high-k dielectric for semiconductor devices The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is per... | 08/05/2008 |
| 7402495 | Method for manufacturing a semiconductor device A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive typ... | 07/22/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7368342 | Semiconductor device and method of manufacturing the same A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, th... | 05/06/2008 |
| 7368356 | Transistor with doped gate dielectric A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped r... | 05/06/2008 |
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat... | 04/29/2008 |
| 7361540 | Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone... | 04/22/2008 |
| 7358567 | High-voltage MOS device and fabrication thereof A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying d... | 04/15/2008 |
| 7358129 | Nonvolatile semiconductor memory device and a method of the same A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, ... | 04/15/2008 |
| 7354817 | Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the g... | 04/08/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7352047 | Systems and methods for integration of heterogeneous circuit devices A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heteroge... | 04/01/2008 |
| 7351628 | Atomic layer deposition of CMOS gates with variable work functions Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween.... | 04/01/2008 |
| 7341930 | Systems and methods for integration of heterogeneous circuit devices A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heteroge... | 03/11/2008 |
| 7335568 | Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors abov... | 02/26/2008 |
| 7332756 | Damascene gate structure with a resistive device A semiconductor structure having a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. The structure includes a first dielectric layer having a first opening and a second opening formed on the semiconductor substrate, and one o... | 02/19/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7329910 | Semiconductor substrates and field effect transistor constructions The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise a gate dielectric layer and a conductive metal-comprising layer havin... | 02/12/2008 |
