Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8110462 | Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or bre... | 02/07/2012 |
| 7838358 | Semiconductor device with capacitor and fuse and its manufacture method An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and seco... | 11/23/2010 |
| 7781280 | Semiconductor device with capacitor and fuse and its manufacture method An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and seco... | 08/24/2010 |
| 7666734 | Semiconductor device having a fuse A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse... | 02/23/2010 |
| 7648870 | Method of forming fuse region in semiconductor damascene process A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an ... | 01/19/2010 |
| 7642150 | Techniques for forming shallow junctions Techniques for forming shallow junctions are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for forming shallow junctions. The method may comprise generating an ion beam comprising molecular ions based on one or more ma... | 01/05/2010 |
| 7595235 | Solid electrolytic capacitor, transmission-line device, method of producing the same, and composite electronic component using the same A solid electrolytic capacitor includes a package for a capacitor element including an anode lead portion and a cathode portion. The package includes an insulating resin member which is arranged to cover the capacitor element and which includes hole portions formed ... | 09/29/2009 |
| 7442626 | Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac... | 10/28/2008 |
| 7413936 | Method of forming copper layers A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 08/19/2008 |
| 7402887 | Semiconductor device having fuse area surrounded by protection means A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the firs... | 07/22/2008 |
| 7402464 | Fuse box of semiconductor device and fabrication method thereof A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed on the uppe... | 07/22/2008 |
| 7381594 | CMOS compatible shallow-trench efuse structure and method A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopan... | 06/03/2008 |
| 7368330 | Semiconductor device having fuse circuit on cell region and method of fabricating the same A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is p... | 05/06/2008 |
| 7354805 | Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 04/08/2008 |
| 7353128 | Measurement system optimization Optimizing a measurement system under test (MSUT) is disclosed. In one embodiment, a method includes selecting a first set of adjustable parameters of the MSUT that affect a quality metric for the MSUT, calculating the quality metric over a range of values of each a... | 04/01/2008 |
| 7352050 | Fuse region of a semiconductor region In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a bl... | 04/01/2008 |
| 7344924 | Fuse structures, methods of making and using the same, and integrated circuits including the same A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupl... | 03/18/2008 |
| 7335537 | Method of manufacturing semiconductor device including bonding pad and fuse elements A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, de... | 02/26/2008 |
| 7313779 | Method and system for tiling a bias design to facilitate efficient design rule checking A method and system for tiling a bias design for an integrated circuit device to facilitate efficient design rule checking. The method is implemented in a computer implemented design synthesis system. The method includes receiving a circuit netlist, wherein the circ... | 12/25/2007 |
| 7309898 | Method and apparatus for providing noise suppression in an integrated circuit A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails. ... | 12/18/2007 |
| 7305320 | Metrology tool recipe validator using best known methods A method of preparing recipes for operating a metrology tool, each recipe including a set of instructions for measuring dimensions in a microelectronic feature. A database includes a plurality of known instructions with best known methods for measuring different fea... | 12/04/2007 |
| 7268068 | Semiconductor device and manufacturing method thereof A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a... | 09/11/2007 |
| 7265001 | Methods of fabricating semiconductor devices Disclosed are methods of fabricating a semiconductor device, by which the pad and fuse layers play their roles smoothly and to enhance a quality of a final semiconductor device. According to one example, a disclosed method includes forming an insulating layer coveri... | 09/04/2007 |
| 7256465 | Ultra-shallow metal oxide surface channel MOS transistor An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region... | 08/14/2007 |
| 7242072 | Electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 07/10/2007 |
| 7180102 | Method and apparatus for using cobalt silicided polycrystalline silicon for a one time programmable non-volatile semiconductor memory A fusible link formed on a semiconductor substrate. The fusible link comprises a silicide layer overlying a polysilicon layer. The fusible link is programmed to an open state by passing a current therethrough that opens the polysilicon and the silicide layers. ... | 02/20/2007 |
| 7176551 | Fuse structure for a semiconductor device A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and lower insulating layers. The fuse layer is connected to the other metal layers through the via plugs. The fuse layer includes at least two separat... | 02/13/2007 |
| 7135369 | Atomic layer deposited ZrAlO dielectric layers including ZrAlO An atomic layer deposited ZrAlxOy dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a zirconium-c... | 11/14/2006 |
| 7135758 | Surface mount solder method and apparatus for decoupling capacitance and process of making A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling... | 11/14/2006 |
| 7132696 | Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a pluralit... | 11/07/2006 |
| 7115966 | Semiconductor device On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide f... | 10/03/2006 |
| 7105917 | Semiconductor device having a fuse connected to a pad and fabrication method thereof A semiconductor device and a fabrication method thereof are provided. The semiconductor device has a probing pad formed on a chip. The probing pad is connected to an output pad and an internal circuit though a fuse. After an electrical testing of the chip by the pro... | 09/12/2006 |
| 7101748 | Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of... | 09/05/2006 |
| 7087974 | Semiconductor integrated circuit including anti-fuse and method for manufacturing the same An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, the... | 08/08/2006 |
| 7079412 | Programmable MOS device formed by stressing polycrystalline silicon A programmable memory circuit and a method for programming the same are disclosed. A polycrystalline silicon resistor pair are used in a programmable memory cell. The pair includes a first polycrystalline silicon resistor stressable by a predetermined current therea... | 07/18/2006 |
| 7067897 | Semiconductor device A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse ... | 06/27/2006 |
| 7067359 | Method of fabricating an electrical fuse for silicon-on-insulator devices A method and apparatus for providing an electrical fuse is provided. An electrical fuse is patterned from the active layer of a semiconductor-on-insulator (SOI) wafer. One shape of the electrical fuse may be a first and second portion electrically coupled via a thir... | 06/27/2006 |
| 7038319 | Apparatus and method to reduce signal cross-talk A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal... | 05/02/2006 |
| 7033900 | Protection of integrated circuit gates during metallization processes In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup... | 04/25/2006 |
| 7005727 | Low cost programmable CPU package/substrate A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 02/28/2006 |
