Class 438/212 - Vertical channel

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making complementary insulated gate field effect
No. of patents: 293
Last issue date: 05/15/2012

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Number	Title	Issue Date
8178403	Method of producing precision vertical and horizontal layers in a vertical semiconductor structure The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (...	05/15/2012
8148222	Cross-point diode arrays and methods of manufacturing cross-point diode arrays Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pil...	04/03/2012
8088657	Integrated circuit using FinFETs and having a static random access memory (SRAM) An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has ...	01/03/2012
8084316	Method of fabricating single transistor floating-body DRAM devices having vertical channel transistor structures Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are dispo...	12/27/2011
8030153	High voltage TMOS semiconductor device with low gate charge structure and method of making A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconduc...	10/04/2011
8017468	Semiconductor device manufacturing method, and semiconductor device A method of manufacturing a semiconductor device in which the formation of buried wiring is facilitated includes: forming columnar patterns, which are arranged in a two-dimensional array, and bridge patterns, which connect the columnar patterns in a column direction...	09/13/2011
8003457	Fabricating method of vertical transistor A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and th...	08/23/2011
7972920	Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor laye...	07/05/2011
7955922	Manufacturing method of fin-type field effect transistor A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching ...	06/07/2011
7902017	Process of forming an electronic device including a trench and a conductive structure therein A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced ap...	03/08/2011
7892912	Method for forming vertical channel transistor of semiconductor device A method for forming a vertical channel transistor of a semiconductor device includes forming a plurality of pillar patterns over a substrate, forming a gate insulation layer encapsulating the resultant pillar pattern structure, forming a surrounding gate electrode ...	02/22/2011
7807526	Method of fabricating high-density, trench-based non-volatile random access SONOS memory cells for SOC applications The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in w...	10/05/2010
7803677	Manufacturing method of semiconductor device A method of manufacturing a semiconductor device, particularly a vertical transistor, including forming a contact hole and forming a pillar using an epitaxial growth process. ...	09/28/2010
7785955	CMOS structure and method including multiple crystallographic planes A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second me...	08/31/2010
7759186	Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices Methods for producing a junction termination extension surrounding the edge of a cathode or anode junction in a semiconductor substrate, where the junction termination extension has a controlled arbitrary lateral doping profile and a controlled arbitrary lateral wid...	07/20/2010
7754560	Integrated circuit using FinFETs and having a static random access memory (SRAM) An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has ...	07/13/2010
7691699	Transistor for semiconductor device and method of forming the same Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed o...	04/06/2010
7666733	Method for making a vertical MOS transistor with embedded gate According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembl...	02/23/2010
7645661	Semiconductor device A semiconductor device manufactured by forming a plurality of first trenches in each of which a trench gate is formed, in an epitaxial layer of a first conductivity type; implanting an impurity of a second conductivity type into a part beneath each of the first tren...	01/12/2010
7635622	Method for manufacturing a vertical transistor that includes a super junction structure A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second colum...	12/22/2009
7625793	Power MOS device with improved gate charge performance A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applie...	12/01/2009
7563665	Semiconductor device and method for manufacturing semiconductor device To laminate field effect transistors having different conductivity types, while suppressing deterioration of the crystallinity of semiconductor layers where the field effect transistors are formed. A single crystal semiconductor layer, a dielectric layer and a singl...	07/21/2009
7465622	Method for making a raised vertical channel transistor device A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form dr...	12/16/2008
7462532	Method of fabricating high voltage metal oxide semiconductor device A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped regio...	12/09/2008
7436022	Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of...	10/14/2008
7432145	Power semiconductor device with a base region and method of manufacturing same A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). ...	10/07/2008
7432134	Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme...	10/07/2008
7429523	Method of forming schottky diode with charge balance structure a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrod...	09/30/2008
7375408	Fabricating method of a high voltage metal oxide semiconductor device A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped regio...	05/20/2008
7374990	Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and alig...	05/20/2008
7372091	Selective epitaxy vertical integrated circuit components Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of t...	05/13/2008
7368353	Trench power MOSFET with reduced gate resistance A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof. ...	05/06/2008
7364997	Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et...	04/29/2008
7358568	Low resistance semiconductor process and structures A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitri...	04/15/2008
7352025	Semiconductor memory device with increased node capacitance An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without ...	04/01/2008
7352034	Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be inte...	04/01/2008
7341896	Method of manufacturing a vertical MOS transistor In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. A first insulating film is deposited over the main ...	03/11/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7332418	High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f...	02/19/2008
7332386	Methods of fabricating fin field transistors A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides ...	02/19/2008

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Class 438/212 - Vertical channel