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| Number | Title | Issue Date |
| 8163610 | Fabrication of finned memory arrays Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper sur... | 04/24/2012 |
| 8084315 | Method of fabricating non-volatile semiconductor memory device by using plasma film-forming method and plasma nitridation A technique capable of improving the memory retention characteristics of a non-volatile memory is provided. In particular, a technique of fabricating a non-volatile semiconductor memory device is provided capable of enhancing the film quality of a silicon oxide film... | 12/27/2011 |
| 8008146 | Different thickness oxide silicon nanowire field effect transistors A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a firs... | 08/30/2011 |
| 7998804 | Nonvolatile memory device including nano dot and method of fabricating the same A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide ... | 08/16/2011 |
| 7968399 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, f... | 06/28/2011 |
| 7871879 | Method of manufacturing semiconductor memory device A method of manufacturing a semiconductor memory device includes forming a device separation film on a semiconductor substrate using a mask pattern for defining an entire source line region as an active region to separate a device separation region from an active re... | 01/18/2011 |
| 7855112 | Fabrication method of pixel structure A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a ... | 12/21/2010 |
| 7851294 | Nanotube memory cell with floating gate based on passivated nanoparticles and manufacturing process thereof A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode,... | 12/14/2010 |
| 7851295 | Flash memory device and method of manufacturing the same A flash memory device and a method of manufacturing a flash memory device are provided. The flash memory device includes a gate region on a semiconductor substrate, spacers on sidewalls of the gate region, and a passivation layer between the semiconductor substrate ... | 12/14/2010 |
| 7795087 | Ultra-violet protected tamper resistant embedded EEPROM A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric st... | 09/14/2010 |
| 7790543 | Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a chan... | 09/07/2010 |
| 7754559 | Method for fabricating capacitor structures using the first contact metal A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided... | 07/13/2010 |
| 7736967 | Method and structure of an one time programmable memory device in an embedded EEPROM A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first ... | 06/15/2010 |
| 7718484 | Method of forming a dielectic film that contains silicon, oxygen and nitrogen and method of fabricating a semiconductor device that uses such a dielectric film In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silic... | 05/18/2010 |
| 7700428 | Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first sem... | 04/20/2010 |
| 7696035 | Method for fabricating non-volatile memory with boost structures A method for fabricating a non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boost... | 04/13/2010 |
| 7651904 | Methods of fabricating non-volatile memory devices including nanocrystals Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel ... | 01/26/2010 |
| 7622343 | Laser processing method, method for forming a flash memory, insulated gate semiconductor device and method for forming the same A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type opposite to s... | 11/24/2009 |
| 7608500 | Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating... | 10/27/2009 |
| 7585721 | Process and apparatus for fabricating nano-floating gate memories and memory made thereby In a process for fabricating a nano-floating gate memory structure, a substrate and a nanocluster source are firstly provided. The nanocluster source is activated for generating a beam of nanoclusters towards the substrate, and at least part of the nanoclusters are ... | 09/08/2009 |
| 7572693 | Methods for transistor formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a... | 08/11/2009 |
| 7550341 | High density stepped, non-planar flash memory A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series... | 06/23/2009 |
| 7550342 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device whose gate structure of a transistor other than a memory cell transistor has a same stacked gate structure as the memory cell transistor, the gate structure comprising a semiconductor substrate, a first insulation film provi... | 06/23/2009 |
| 7531404 | Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the ... | 05/12/2009 |
| 7524719 | Method of making self-aligned split gate memory cell A method for forming a split gate memory cell (10,11) using a semiconductor substrate (12) includes forming a select gate structure (48) and a sacrificial structure (50) over the substrate. An opening is between the select gate structure ... | 04/28/2009 |
| 7517749 | Method for forming an array with polysilicon local interconnects Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present inventio... | 04/14/2009 |
| 7517750 | Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart... | 04/14/2009 |
| 7514311 | Method of manufacturing a SONOS memory A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A... | 04/07/2009 |
| 7494861 | Method for metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 02/24/2009 |
| 7462531 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, f... | 12/09/2008 |
| 7452766 | Finned memory cells and the fabrication thereof Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper sur... | 11/18/2008 |
| 7445984 | Method for removing nanoclusters from selected regions A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma ni... | 11/04/2008 |
| 7439131 | Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r... | 10/21/2008 |
| 7439567 | Contactless nonvolatile memory array An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe... | 10/21/2008 |
| 7439121 | Dielectric film and method of forming it, semiconductor device, non-volatile semiconductor memory device, and production method for semiconductor device In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silic... | 10/21/2008 |
| 7436017 | Semiconductor integrated circuit using a selective disposable spacer Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions be... | 10/14/2008 |
| 7432158 | Method for retaining nanocluster size and electrical characteristics during processing A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first p... | 10/07/2008 |
| 7429511 | Method of forming a tunneling insulating layer in nonvolatile memory device A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate,... | 09/30/2008 |
| 7422939 | Semiconductor device having one-time programmable ROM and method of fabricating the same A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and ... | 09/09/2008 |
| 7419865 | Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sac... | 09/02/2008 |
