Class 438/208 - Isolation by PN junction only

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making complementary insulated gate field effect
No. of patents: 62
Last issue date: 12/29/2009

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Number	Title	Issue Date
7638385	Method of forming a semiconductor device and structure therefor A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die. ...	12/29/2009
7462530	Method for manufacturing a semiconductor device having an element isolation region An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An ...	12/09/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7247921	Semiconductor apparatus and method of manufacturing same, and method of detecting defects in semiconductor apparatus A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semic...	07/24/2007
7173316	Semiconductor device An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to ele...	02/06/2007
7018866	Circuit component built-in module with embedded semiconductor chip and method of manufacturing A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating...	03/28/2006
7015084	Method of manufacturing a field effect transistor and a liquid crystal display using the same A gate-overlap-drain structure is obtained by a single pair of a single impurity implantation process and a single laser anneal process, wherein the improved gate-overlap-drain structure includes lightly activated high impurity concentration regions exhibiting subst...	03/21/2006
6974999	Semiconductor device and method of manufacturing the same It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard ma...	12/13/2005
6943072	Adjustable threshold isolation transistor An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isola...	09/13/2005
6927460	Method and structure for BiCMOS isolated NMOS transistor A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with ...	08/09/2005
6909150	Mixed signal integrated circuit with improved isolation An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit furt...	06/21/2005
6841437	Method of forming a vertical power semiconductor device and structure therefor A method of forming medium breakdown voltage vertical transistors (11) and lateral transistors (12, 13) on the same substrate (14) provides for optimizing the epitaxial layer (16) for the lateral transistors (12, 13). The vertical ...	01/11/2005
6787880	ESD parasitic bipolar transistors with high resistivity regions in the collector A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions ...	09/07/2004
6784043	Methods for forming aligned fuses disposed in an integrated circuit An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and...	08/31/2004
6781206	Semiconductor device with structure restricting flow of unnecessary current therein Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P− substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-...	08/24/2004
6653182	Process for forming deep and shallow insulative regions of an integrated circuit Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coa...	11/25/2003
6630377	Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reach...	10/07/2003
6624497	Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of dif...	09/23/2003
6589833	ESD parasitic bipolar transistors with high resistivity regions in the collector A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silici...	07/08/2003
6582997	ESD protection scheme for outputs with resistor loading Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal c...	06/24/2003
6541325	Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so t...	04/01/2003
6521493	Semiconductor device with STI sidewall implant A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semicond...	02/18/2003
6472712	Semiconductor device with reduced transistor leakage current A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both ...	10/29/2002
6362036	VDMOS transistor protected against over-voltages between source and gate The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed ...	03/26/2002
6201293	Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same The present invention relates to electro optical devices with a reduced filter thinning on the edge pixels and a method for reducing the thinning of filter layers on the pixels closest to the edge of an electro optical device such as a photosensitive chip...	03/13/2001
6051457	Method for fabricating electrostatic discharge protection device An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the catho...	04/18/2000
6010926	Method for forming multiple or modulated wells of semiconductor device The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention,...	01/04/2000
5899714	Fabrication of semiconductor structure having two levels of buried regions Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated...	05/04/1999
5880002	Method for making isolated vertical PNP transistor in a digital BiCMOS process A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is...	03/09/1999
5856218	Bipolar transistor formed by a high energy ion implantation method In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement ...	01/05/1999
5776807	Method for fabricating a triple well for bicmos devices To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has...	07/07/1998
5702959	Method for making an isolated vertical transistor A process for making a vertical PNP transistor and a transistor made by the process includes providing a highly doped semiconductor substrate (10) of P conductivity type. A first lightly doped P- layer (12) is epitaxially grown on the substrate (10). An N...	12/30/1997
5591657	Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking The invention increases withstand voltage and current capacity of a DMOS portion simultaneously built in by the BiCMOS process. The manufacturing method for the DMOS portion is comprised of steps of forming an ion-implanted layer in a surface of a P-type ...	01/07/1997
5580798	Method of fabricating bipolar transistor having a guard ring In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitax...	12/03/1996
5556796	Self-alignment technique for forming junction isolation and wells A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to def...	09/17/1996
5470766	Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substr...	11/28/1995
5371023	Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic l...	12/06/1994
5290714	Method of forming semiconductor device including a CMOS structure having double-doped channel regions A semiconductor device has, in one embodiment, a p type insulated gate field effect transistor formed in an n type well formed on a semiconductor substrate and an n type insulated gate field effect transistor formed in a p type well formed on the semicond...	03/01/1994
5268312	Method of forming isolated wells in the fabrication of BiCMOS devices A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type b...	12/07/1993
5262345	Complimentary bipolar/CMOS fabrication method A complementary bipolar process enables both PNP and NPN transistors to be added to a CMOS process with a minimum of extra fabrication steps. The P-well of a CMOS process is used for the collector region of the PNP transistor and the "down isolation" for ...	11/16/1993

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Class 438/208 - Isolation by PN junction only