Class 438/206 - Vertical channel insulated gate field effect transistor

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making complementary insulated gate field effect
No. of patents: 139
Last issue date: 05/01/2012

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Number	Title	Issue Date
8168492	Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a pe...	05/01/2012
8003456	Method for producing a semiconductor component A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the t...	08/23/2011
7932142	Transistor in a wiring interlayer insulating film A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lo...	04/26/2011
7923320	Methods of fabricating vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on...	04/12/2011
7915113	Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device including a vertical cell transistor structure may include forming a vertical cell transistor structure over a semiconductor substrate of a cell region; forming an insulating film over the vertical cell transistor st...	03/29/2011
7892911	Metal gate electrodes for replacement gate integration scheme Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of ...	02/22/2011
7851293	Method for forming vertical channel transistor of semiconductor device A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pil...	12/14/2010
7674669	FIN field effect transistor Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickn...	03/09/2010
7642149	Method for producing semiconductor device A method for producing a semiconductor device which includes: a semiconductor base, a hetero semiconductor region made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base, and so configured as to form a hetero j...	01/05/2010
7432134	Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme...	10/07/2008
7427788	Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating regio...	09/23/2008
7410856	Methods of forming vertical transistors A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming...	08/12/2008
7402483	Methods of forming a multi-bridge-channel MOSFET A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenc...	07/22/2008
7371588	Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device includes: forming a circuit element on a semiconductor substrate; forming a first insulation film on top to cover the circuit element; forming a first electrode on top; forming a ferroelectric film on the first electr...	05/13/2008
7358141	Semiconductor device and method for fabricating the same Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of ...	04/15/2008
7341896	Method of manufacturing a vertical MOS transistor In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. A first insulating film is deposited over the main ...	03/11/2008
7341905	Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of sixteen specific mask steps that permit a variety of bipolar/CMOS/DMOS devices to be fabr...	03/11/2008
7329570	Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, ...	02/12/2008
7313863	Method to form a cavity having inner walls of varying slope An improved mold, for use in the formation of a perpendicular magnetic write head, is described, together with a process for its manufacture. Conventional alumina is replaced by tantalum in the yoke portion of the mold. When both the tantalum and the alumina areas a...	01/01/2008
7303967	Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an...	12/04/2007
7288815	Semiconductor device and manufacturing method thereof A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different fr...	10/30/2007
7288451	Method and structure for forming self-aligned, dual stress liner for CMOS devices A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of th...	10/30/2007
7279399	Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	10/09/2007
7276775	Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an...	10/02/2007
7271497	Dual metal stud bumping for flip chip applications A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed t...	09/18/2007
7271052	Long retention time single transistor vertical memory gain cell A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lowe...	09/18/2007
7265434	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	09/04/2007
7256086	Trench lateral power MOSFET and a method of manufacturing the same A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional...	08/14/2007
7247532	High voltage transistor and method for fabricating the same A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−...	07/24/2007
7242059	Semiconductor device having DMOS and CMOS on single substrate A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a ...	07/10/2007
7235857	Power semiconductor device A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to ...	06/26/2007
7214985	Integrated circuit incorporating higher voltage devices and low voltage devices therein An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a transistor having a gate located over a channel region recessed into ...	05/08/2007
7211863	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	05/01/2007
7202536	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	04/10/2007
7196376	Trench-type power MOSFET with embedded region at the bottom of the gate and increased breakdown voltage An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source el...	03/27/2007
7192872	Method of manufacturing semiconductor device having composite buffer layer The present invention relates to a method of manufacturing semiconductor device with composite buffer layers. The method includes etching grooves in n type and p type semiconductor wafers respectively. The areas of grooves in n type wafer just correspond to the area...	03/20/2007
7189648	Method for reducing the contact resistance of the connection regions of a semiconductor device One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal c...	03/13/2007
7176527	Semiconductor device and method of fabricating same A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insu...	02/13/2007
7173306	Vertical semiconductor component having a drift zone having a field electrode, and method for fabricating such a drift zone The invention relates to a method for fabricating a drift zone of a vertical semiconductor component and to a vertical semiconductor component having the following features: a semiconductor body (100) having a first side (	02/06/2007
7169660	Lithography-independent fabrication of small openings for forming vertical mos transistor A method for formation of openings in semiconducting devices not limited by constraints of photolithography include forming a first dielectric layer over a semiconducting substrate, depositing a polysilicon layer over the first dielectric layer, forming a second die...	01/30/2007

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Class 438/206 - Vertical channel insulated gate field effect transistor