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"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
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| Number | Title | Issue Date |
| 8129234 | Method of forming bipolar transistor integrated with metal gate CMOS devices A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor s... | 03/06/2012 |
| 8071436 | Method of fabricating a semiconductor device having a lateral double diffused MOSFET transistor with a lightly doped source and CMOS transistor Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. In some implementations, a method... | 12/06/2011 |
| 7981739 | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into t... | 07/19/2011 |
| 7666731 | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into t... | 02/23/2010 |
| 7465621 | Method of fabricating a switching regulator with a high-side p-type device A first impurity region of a first type is implanted to have a first surface area on a substrate. A second impurity region of an opposite second type is implanted into a drain region of the transistor to have a second surface area in the first surface area of the fi... | 12/16/2008 |
| 7381606 | Semiconductor device and method of forming a semiconductor device A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provide... | 06/03/2008 |
| 7364960 | Methods for fabricating solid state image sensor devices having non-planar transistors Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current. ... | 04/29/2008 |
| 7358573 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 04/15/2008 |
| 7344935 | Method of manufacturing a semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one emb... | 03/18/2008 |
| 7291882 | Programmable and erasable digital switch device and fabrication method and operating method thereof A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge sto... | 11/06/2007 |
| 7285454 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 10/23/2007 |
| 7238971 | Self-aligned lateral heterojunction bipolar transistor A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer... | 07/03/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7217609 | Semiconductor fabrication process, lateral PNP transistor, and integrated circuit A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around ... | 05/15/2007 |
| 7214558 | Method for forming patterns on a semiconductor device using a lift off technique Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a ... | 05/08/2007 |
| 7176527 | Semiconductor device and method of fabricating same A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insu... | 02/13/2007 |
| 7173320 | High performance lateral bipolar transistor A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bia... | 02/06/2007 |
| 7163856 | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into t... | 01/16/2007 |
| 7132344 | Super self-aligned BJT with base shorted field plate and method of fabricating A bipolar junction transistor (BJT) structure and fabrication method are provided in which a doped polysilicon filled trench is utilized to form both the extrinsic base contact region and a vertical field plate. A sacrificial mandrel of dielectric material is formed... | 11/07/2006 |
| 7115460 | Standard cell back bias architecture An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transist... | 10/03/2006 |
| 7084001 | Method of forming film including a comb tooth patterning film Resist patterns (R11 and R12) are formed such that an opening between both the films is aligned to the position, where the source electrode (7) is formed, while the region on the N+-layer (5), where the drain electrode (8 | 08/01/2006 |
| 7075152 | Semiconductor storage device A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a sourc... | 07/11/2006 |
| 7056816 | Method for manufacturing semiconductor device A mask layer having an opening is formed on a semiconductor substrate. Next, oxygen ions and a first impurity are implanted into the semiconductor substrate using the mask layer as a mask. Then, the mask layer is removed. Next, the oxygen ions are heat treated to re... | 06/06/2006 |
| 7029938 | Method for forming patterns on a semiconductor device using a lift off technique Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa is formed, followed by successive formation of ... | 04/18/2006 |
| 7001806 | Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor are... | 02/21/2006 |
| 6987039 | Forming lateral bipolar junction transistor in CMOS flow A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall depo... | 01/17/2006 |
| 6963090 | Enhancement mode metal-oxide-semiconductor field effect transistor An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial ma... | 11/08/2005 |
| 6927460 | Method and structure for BiCMOS isolated NMOS transistor A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with ... | 08/09/2005 |
| 6914012 | Article comprising an oxide layer on a GaAs-based semiconductor structure and method of forming same A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor s... | 07/05/2005 |
| 6875648 | Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approxi... | 04/05/2005 |
| 6815282 | Silicon on insulator field effect transistor having shared body contact Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetr... | 11/09/2004 |
| 6794237 | Lateral heterojunction bipolar transistor A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (... | 09/21/2004 |
| 6784065 | Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow throug... | 08/31/2004 |
| 6767779 | Asymmetrical MOSFET layout for high currents and high speed operation A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers th... | 07/27/2004 |
| 6750109 | Halo-free non-rectifying contact on chip with halo source/drain diffusion A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion... | 06/15/2004 |
| 6692994 | Method for manufacturing a programmable chalcogenide fuse within a semiconductor device A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on ... | 02/17/2004 |
| 6667202 | Semiconductor device and method for making the same A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the su... | 12/23/2003 |
| 6638824 | Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage A double-diffused metal-oxide-semiconductor ("DMOS") field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the sourc... | 10/28/2003 |
| 6616786 | Process for applying an ink-only label to a polymeric surface The invention is directed to a returnable plastic crate provided on at least one surface with an ink only label that is removable without destructive treatment of the said surface, said label being adhered to said at least one surface by an activated adhe... | 09/09/2003 |
| 6570240 | Semiconductor device having a lateral bipolar transistor and method of manufacturing same In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film i... | 05/27/2003 |
