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| Number | Title | Issue Date |
| 7521310 | Vertical thyristor in complementary SiGe bipolar process In a complementary SiGe bipolar process, a pnpn thyristor structure is formed from some of the layers of a pnp transistor and an npn transistor formed on top of each other and making use of the SiGe gates to define the blocking junction. ... | 04/21/2009 |
| 7439140 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 10/21/2008 |
| 7368345 | Flash memory devices and methods of fabricating the same Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portio... | 05/06/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7348256 | Methods of forming reduced electric field DMOS using self-aligned trench isolation A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon di... | 03/25/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7329570 | Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, ... | 02/12/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7319263 | Semiconductor component with switching element configured to reduce parasitic current flow A semiconductor component is described. In one embodiment, the semiconductor component includes a switching element integrated in the semiconductor component between two functional element semiconductor regions, configured to reduce a parasitic current flow through ... | 01/15/2008 |
| 7314791 | Bipolar transistor for an integrated circuit having variable value emitter ballast resistors An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for ea... | 01/01/2008 |
| 7282401 | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and... | 10/16/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7271044 | CMOS (complementary metal oxide semiconductor) technology A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the... | 09/18/2007 |
| 7265010 | High performance vertical PNP transistor method The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, an... | 09/04/2007 |
| 7265012 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 09/04/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7253485 | Semiconductor device and manufacturing method thereof A manufacturing method for a CMOS semiconductor device in which gate electrodes are adjusted to have different work function values comprises forming an device region of a first and second conductivity type for forming first and second MOS semiconductor element devi... | 08/07/2007 |
| 7247532 | High voltage transistor and method for fabricating the same A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−... | 07/24/2007 |
| 7235822 | Transistor with silicon and carbon layer in the channel region A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the transistor. A layer of silicon and carbon is epitaxially grown in the channel region. A thin semiconductor mat... | 06/26/2007 |
| 7232733 | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of ... | 06/19/2007 |
| 7229870 | Methods of fabricating semiconductor devices Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the ... | 06/12/2007 |
| 7230342 | Registration mark within an overlap of dopant regions A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack ... | 06/12/2007 |
| 7226826 | Semiconductor device having multiple work functions and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over... | 06/05/2007 |
| 7220633 | Method of fabricating a lateral double-diffused MOSFET A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity regi... | 05/22/2007 |
| 7211863 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 05/01/2007 |
| 7202536 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 04/10/2007 |
| 7189607 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 03/13/2007 |
| 7187056 | Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo... | 03/06/2007 |
| 7176483 | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin ... | 02/13/2007 |
| 7164174 | Single poly-emitter PNP using dwell diffusion in a BiCMOS technology A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one... | 01/16/2007 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7141858 | Dual work function CMOS gate technology based on metal interdiffusion A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the m... | 11/28/2006 |
| 7135738 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 11/14/2006 |
| 7126190 | Self-aligned gate and method A semiconductor structure includes a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by fir... | 10/24/2006 |
| 7118998 | Method of forming a conductive structure A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bott... | 10/10/2006 |
| 7105398 | Method for monitoring lateral encroachment of spacer process on a CD SEM A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measu... | 09/12/2006 |
| 7098094 | NiSi metal gate stacks using a boron-trap A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that r... | 08/29/2006 |
