Class 438/202 - Including bipolar transistor (i.e., BiCMOS)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making complementary insulated gate field effect
No. of patents: 463
Last issue date: 05/08/2012

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Number	Title	Issue Date
8173500	Poly-emitter type bipolar junction transistor, bipolar CMOS DMOS device, and manufacturing methods of poly-emitter type bipolar junction transistor and bipolar CMOS DMOS device A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a ba...	05/08/2012
8124468	Process of forming an electronic device including a well region An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to ...	02/28/2012
8058121	Method for fabricating semiconductor device, method for fabricating bipolar-CMOS-DMOS A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the differe...	11/15/2011
8030151	Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length A bipolar transistor (101) has a base (243) formed with an intrinsic base portion (2431), a base contact portion (245C), and a base link portion (243L) that extends between the intrinsic base portion and the base contact portion. An isolating dielectric layer (267-1...	10/04/2011
7972919	Vertical PNP transistor and method of making same The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrins...	07/05/2011
7939402	Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors and manufacturing method A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified proc...	05/10/2011
7892910	Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS ...	02/22/2011
7883954	Self-aligned epitaxially grown bipolar transistor The illumination system has a light source (1) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the f...	02/08/2011
7875513	Self-aligned bipolar junction transistors A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact reg...	01/25/2011
7846789	Isolation trench with rounded corners for BiCMOS process A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transis...	12/07/2010
7829405	Lateral bipolar transistor with compensated well regions Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield...	11/09/2010
7772060	Integrated SiGe NMOS and PMOS transistors A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a M...	08/10/2010
7696034	Methods of base formation in a BiCOMS process Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silic...	04/13/2010
7645659	Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. H...	01/12/2010
7635621	Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Rarea product A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region tou...	12/22/2009
7625792	Method of base formation in a BiCMOS process Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shap...	12/01/2009
7579230	High voltage BICMOS device and method for manufacturing the same A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) r...	08/25/2009
7569448	Semiconductor device including bipolar junction transistor with protected emitter-base junction A method of manufacturing a CMOS-BJT semiconductor device comprises the steps of: forming a collector region of a first conductivity type and a first well of the first conductivity type, simultaneously in a semiconductor substrate; forming a second well of a second ...	08/04/2009
7534680	Bipolar transistor, BiCMOS device, and method for fabricating thereof Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT is removed and a collector plug disposed at a lateral side of the collector is approached to a base when f...	05/19/2009
7534679	System and method for producing a semiconductor circuit arrangement Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and...	05/19/2009
7524718	Method for manufacturing photoelectric transducer, and electronic apparatus A method for manufacturing a photoelectric transducer, comprising: forming a first electrode on a substrate; forming a first conductivity-type semiconductor layer on the first electrode; forming an I type semiconductor layer on the first conductivity-type semiconduc...	04/28/2009
7488638	Method for fabricating a voltage-stable PMOSFET semiconductor structure A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate f...	02/10/2009
7456061	Method to reduce boron penetration in a SiGe bipolar device The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bip...	11/25/2008
7442602	Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower r...	10/28/2008
7427542	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; rem...	09/23/2008
7415318	Method and apparatus for manufacturing semiconductor device Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer diele...	08/19/2008
7393739	Demultiplexers using transistors for accessing memory cell arrays A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in...	07/01/2008
7384836	Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel...	06/10/2008
7372155	Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an ...	05/13/2008
7371650	Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and...	05/13/2008
7368822	Copper metalized ohmic contact electrode of compound device The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resis...	05/06/2008
7365440	Semiconductor device and fabrication method thereof A semiconductor device includes a second insulating film formed on a second surface of a semiconductor substrate whose first surface has been formed with a first insulating film and an electrode pad, and an opening is made in a portion of the second insulating film ...	04/29/2008
7358573	Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin...	04/15/2008
7354840	Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer...	04/08/2008
7348124	High-density readable only optical disk A high-density readable only optical disk with a large storage capacity includes a substrate with pits, and one or more mask layers with a super resolution near field structure, which are made of a mixture of a dielectric material and metal particles. The optical di...	03/25/2008
7344989	CMP wafer contamination reduced by insitu clean Reducing CMP wafer contamination by in-situ clean is disclosed herein. The invention can be employed in a method in which a conductive layer is formed on a surface of a semiconductor wafer. After a portion of the conductive layer is removed, an acidic solution is di...	03/18/2008
7341905	Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of sixteen specific mask steps that permit a variety of bipolar/CMOS/DMOS devices to be fabr...	03/11/2008
7341915	Method of making planar double gate silicon-on-insulator structures Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed...	03/11/2008
7338848	Method for opto-electronic integration on a SOI substrate and related structure According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer...	03/04/2008
7339254	SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed...	03/04/2008

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Class 438/202 - Including bipolar transistor (i.e., BiCMOS)