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| Number | Title | Issue Date |
| 8110460 | Method for producing stacked and self-aligned components on a substrate A method for producing stacked and self-aligned components on a substrate, including: providing a substrate made of monocrystalline silicon having one face enabling production of components, forming a stack of layers on the face of the substrate, selective etching b... | 02/07/2012 |
| 8088656 | Fabricating ESD devices using MOSFET and LDMOS A method, including; simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate; and simultaneously forming a thir... | 01/03/2012 |
| 8067279 | Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat... | 11/29/2011 |
| 7838357 | Optoelectronic component Optoelectronic component, having a housing body (2), an optoelectronic semiconductor chip (3) arranged in a recess (6) of the housing body, and having electrical terminals (1A, 1B), the semiconductor chip being electrically conduct... | 11/23/2010 |
| 7776676 | Fabricating method of complementary metal-oxide-semiconductor (CMOS) image sensor including p type gate structure A method of fabricating a complementary metal-oxide-semiconductor image sensor is provided. First, a substrate having a photo sensitive region and a transistor device region is provided. A p type well in the substrate of the transistor device region is formed. A die... | 08/17/2010 |
| 7718482 | CD gate bias reduction and differential N+ poly doping for CMOS circuits A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is ... | 05/18/2010 |
| 7713808 | CMOS image sensor and method for fabricating the same A complementary metal oxide semiconductor (CMOS) image sensor (CIS) and a method for fabricating the same. A method for fabricating a CIS includes implanting first conductive type dopants in a semiconductor substrate to form a photodiode region in a surface of the s... | 05/11/2010 |
| 7704820 | Fabricating method of metal line A method of fabricating a metal line using a dual damascene process which enhances reliability of the semiconductor device. The method includes forming a lower metal line in a first inter metal dielectric layer; and then sequentially forming a first anti-etch layer,... | 04/27/2010 |
| 7651903 | CMOS image sensor and method for manufacturing the same Disclosed are a CMOS image sensor and a method for manufacturing the same, for reducing or preventing damage to a photodiode and improving a pixel design margin to achieve scale down of a pixel. The CMOS image sensor includes an isolation layer in a semiconductor su... | 01/26/2010 |
| 7642148 | Methods of producing semiconductor devices including multiple stress films in interface area A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first ... | 01/05/2010 |
| 7611940 | CMOS image sensor and manufacturing method thereof Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes forming an isolation layer in a semiconductor substrate, defining an active region including a photo diode region and a transistor region; forming a gate insulating layer and a... | 11/03/2009 |
| 7601580 | Image sensor and method of fabricating the same An image sensor may include a semiconductor substrate having a pixel array region and a logic region. A first gate electrode may be formed on the pixel array region of the semiconductor substrate. A lower electrode may be formed on a portion of the logic region of t... | 10/13/2009 |
| 7598134 | Memory device forming methods A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes... | 10/06/2009 |
| 7598135 | Method for fabricating CMOS image sensor Provided is a method for fabricating CMOS image sensor. One method includes: preparing a semiconductor substrate in which a photodiode region and a transistor region are defined; sequentially forming an insulating layer and a conductive layer on an entire surface of... | 10/06/2009 |
| 7588978 | Method for forming semiconductor device Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and low-voltage (LV) wells, the first oxide layer having a predetermined thickness... | 09/15/2009 |
| 7582522 | Method and device for CMOS image sensing with separate source formation A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region ... | 09/01/2009 |
| 7560330 | CMOS image sensor and method for manufacturing the same A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active r... | 07/14/2009 |
| 7556998 | Method of manufacturing semiconductor devices A method of manufacturing a semiconductor device including forming a dummy gate electrode which is divided into first and second areas, selectively implanting N-type ions and P-type ions into the first and second areas of the dummy gate electrode respectively and th... | 07/07/2009 |
| 7541235 | Method for providing a programmable electrostatic discharge (ESD) protection device A method for providing a programmable electrostatic discharge (ESD) protection device is provided. The method includes providing a source diffusion in a substrate, providing a deeper body diffusion in the substrate, providing a gate at a space between the source dif... | 06/02/2009 |
| 7534678 | Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compre... | 05/19/2009 |
| 7488636 | Broken die detect sensor A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate broken die lands or other malfunctions. ... | 02/10/2009 |
| 7485523 | Method for forming high voltage device and semiconductor device The invention is directed to a method for manufacturing a high voltage device. The method comprises steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a secon... | 02/03/2009 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening se... | 11/18/2008 |
| 7445983 | Method of manufacturing a semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one emb... | 11/04/2008 |
| 7445982 | Method of manufacturing a semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one emb... | 11/04/2008 |
| 7442611 | Method of applying stresses to PFET and NFET transistor channels for improved performance A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semicon... | 10/28/2008 |
| 7442994 | CMOS image sensor and method for manufacturing the same A CMOS image sensor and a method for manufacturing the same improve light-receiving efficiency and maintain a margin in the design of a metal line. The CMOS image sensor includes a transparent substrate including an active area having a photodiode region and a trans... | 10/28/2008 |
| 7413945 | Electrically isolated pillars in active devices A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be per... | 08/19/2008 |
| 7405118 | Semiconductor device and method of fabricating the same The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region throu... | 07/29/2008 |
| 7405101 | CMOS imager with selectively silicided gate The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned... | 07/29/2008 |
| 7405127 | Method for producing a vertical field effect transistor A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electr... | 07/29/2008 |
| 7402864 | Method for forming a DRAM semiconductor device with a sense amplifier A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation int... | 07/22/2008 |
| 7402479 | CMOS image sensor and fabricating method thereof A fabricating method of a CMOS image sensor includes the steps of: forming a transfer gate on a semiconductor substrate where a device isolation layer is formed; forming a first n-type ion implantation region for a photodiode beneath a surface of the semiconductor s... | 07/22/2008 |
| 7402492 | Method of manufacturing a memory device having improved erasing characteristics In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor subst... | 07/22/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7384836 | Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel... | 06/10/2008 |
| 7372200 | Light-emitting device, method of manufacturing a light-emitting device, and electronic equipment The present invention uses plastic film in vacuum sealing an OLED. Inorganic insulating films which can prevent oxygen or water from being penetrated therein and an organic insulating film which has a smaller internal stress than that of the inorganic insulating fil... | 05/13/2008 |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7368313 | Method of making a differential pressure sensor In a method for manufacturing a micromechanical semiconductor component, e.g., a pressure sensor, a locally limited, buried, and at least partially oxidized porous layer is produced in a semiconductor substrate. A cavity is subsequently produced in the semiconductor... | 05/06/2008 |
| 7368331 | Manufacturing method of thin-film transistor, thin-film transistor sheet, and electric circuit A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an isolati... | 05/06/2008 |
