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| Number | Title | Issue Date |
| 8003410 | Method of operating quantum-mechanical memory and computational devices A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the ... | 08/23/2011 |
| 7968352 | Superconductivity based on bose-einstein condensation of electron or electron-hole pairs in semiconductors The invention describes a method of achieving superconductivity in Group IV semiconductors via the addition of doubly charged impurity atoms to the crystal lattice. The doubly charged impurities function as composite bosons in the semiconductor. Increasing the densi... | 06/28/2011 |
| 7829352 | Fabrication of nano-object array This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs. ... | 11/09/2010 |
| 7767469 | Magnetic random access memory and method of manufacturing the same A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape a... | 08/03/2010 |
| 7615385 | Double-masking technique for increasing fabrication yield in superconducting electronics A new technique is presented for improving the microfabrication yield of Josephson junctions in superconducting integrated circuits. This is based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junc... | 11/10/2009 |
| 7560291 | Method for fabrication of high temperature superconductors A layered article of manufacture and a method of manufacturing same is disclosed. A substrate has a biaxially textured MgO crystalline layer having the c-axes thereof inclined with respect to the plane of the substrate deposited thereon. A layer of one or more of YS... | 07/14/2009 |
| 7541198 | Method of forming quantum-mechanical memory and computational devices A method of forming a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external world, is dis... | 06/02/2009 |
| 7371586 | Superconductor and process for producing the same A superconductor and a method for producing the same are provided. The method for producing a superconductor includes the step of forming a superconducting layer on a base layer by performing a film deposition at least three times, wherein the film thickness of a su... | 05/13/2008 |
| 7357018 | Method for performing a measurement inside a specimen using an insertable nanoscale FET probe A measurement inside a specimen is performed by providing a nanoscale FET probe comprising a cantilever element and a nanowire extending from the cantilever element. The nanowire is electrically connected to the cantilever element at at least one of the ends of the ... | 04/15/2008 |
| 7351313 | Production device and production method for conductive nano-wire The object of the present invention is to provide a nano-scale molecular assembly such as a conductive nano-wire. Specifically, there is provided an electrolytic apparatus for forming a molecular assembly, including two electrodes and an electrolytic cell holding an... | 04/01/2008 |
| 7332736 | Article comprising gated field emission structures with centralized nanowires and method for making the same This invention provides novel methods of fabricating novel gated field emission structures that include aligned nanowire electron emitters (individually or in small groups) localized in central regions within gate apertures. It also provides novel devices using nano... | 02/19/2008 |
| 7327037 | High density nanostructured interconnection A method and apparatus for forming an electrically and/or thermally conducting interconnection is disclosed wherein a first surface and a second surface are contacted with each other via a plurality of nanostructures disposed on at least one of the surfaces. In one ... | 02/05/2008 |
| 7323348 | Superconducting integrated circuit and method for fabrication thereof A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order ment... | 01/29/2008 |
| 7323711 | High-temperature superconductive device A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the secon... | 01/29/2008 |
| 7322871 | Process to make nano-structured emitters for incandescence light sources In a process to make an emitter (10) for light sources, which can be led to incandescence through the passage of electric current, a layer made of anodized porous alumina (1) is used as sacrificial element for the structuring of at least a part of the ... | 01/29/2008 |
| 7314765 | Switching device using superlattice without any dielectric barriers A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossov... | 01/01/2008 |
| 7301779 | Electronic chip and electronic chip assembly A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip and a further electronic chip. ... | 11/27/2007 |
| 7294202 | Process for manufacturing self-assembled nanoparticles Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step... | 11/13/2007 |
| 7284690 | Article to be processed having ID, and production method thereof A processed article is provided with a plurality of IDs having the same information for machine reading but difference to be confirmed visually. The information such as the production lot number which is read from the plurality of IDs by the reading device is the sa... | 10/23/2007 |
| 7279432 | System and method for forming an integrated barrier layer An apparatus and method for forming an integrated barrier layer on a substrate is described. The integrated barrier layer comprises at least a first refractory metal layer and a second refractory metal layer. The integrated barrier layer is formed using a dual-mode ... | 10/09/2007 |
| 7276389 | Article comprising metal oxide nanostructures and method for fabricating such nanostructures This invention discloses novel field emitters which exhibit improved emission characteristics combined with improved emitter stability, in particular, new types of carbide or nitride based electron field emitters with desirable nanoscale, aligned and sharped-tip emi... | 10/02/2007 |
| 7270761 | Fluorine free integrated process for etching aluminum including chamber dry clean A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma rea... | 09/18/2007 |
| 7242705 | Grating-outcoupled cavity resonator having uni-directional emission A grating-outcoupled microcavity disk resonator has whispering gallery modes existing in a nearly circular resonator. Light is outcoupled by providing a grating region in the plane of the grating-outcoupled microcavity disk resonator. The grating region provides an ... | 07/10/2007 |
| 7227066 | Polycrystalline optoelectronic devices based on templating technique Methods for passivating crystalline grains in an active layer for an optoelectronic device and optoelectronic devices having active layers with passivated crystalline grains are disclosed. Crystalline grains of an active layer material and/or window layer material a... | 06/05/2007 |
| 7226663 | Method for synthesizing nanoscale structures in defined locations A method is disclosed for directly synthesizing nanoscale structures, particularly in defined locations. The method overcomes problems in nanoscale manufacturing by enabling the direct fabrication of composites useful for constructing electronic devices. In one aspe... | 06/05/2007 |
| 7223611 | Fabrication of nanowires This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be cre... | 05/29/2007 |
| 7220451 | Process for producing metal thin films by ALD Electrically conductive noble metal thin films can be deposited on a substrate by atomic layer deposition. According to one embodiment of the invention a substrate with a surface is provided in a reaction chamber and a vaporised precursor of a noble metal is pulsed ... | 05/22/2007 |
| 7211144 | Pulsed nucleation deposition of tungsten layers A method of forming a tungsten nucleation layer using a sequential deposition process. The tungsten nucleation layer is formed by reacting pulses of a tungsten-containing precursor and a reducing gas in a process chamber to deposit tungsten on the substrate. Thereaf... | 05/01/2007 |
| 7208094 | Methods of bridging lateral nanowires and device using same A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of laterally bridging the nanowire grows the nanowire from the activated ... | 04/24/2007 |
| 7205643 | Stray field shielding structure for semiconductors A stray field shielding structure for die attaching onto a magnetic random access memory chip or to other chips to prevent loss of memory due to magnetic fields or radiation is made by a method which provides a thick layer of magnetic material which is precise in it... | 04/17/2007 |
| 7199498 | Electrical assemblies using molecular-scale electrically conductive and mechanically flexible beams and methods for application of same Electromechanical systems utilizing suspended conducting nanometer-scale beams are provided and may be used in applications, such as, motors, generators, pumps, fans, compressors, propulsion systems, transmitters, receivers, heat engines, heat pumps, magnetic field ... | 04/03/2007 |
| 7196450 | Electromechanical assemblies using molecular-scale electrically conductive and mechanically flexible beams and methods for application of same Electromechanical systems utilizing suspended conducting nanometer-scale beams are provided and may be used in applications, such as, motors, generators, pumps, fans, compressors, propulsion systems, transmitters, receivers, heat engines, heat pumps, magnetic field ... | 03/27/2007 |
| 7186381 | Hydrogen gas sensor A hydrogen gas sensor and/or switch fabricated from arrays nanowires composed of metal or metal alloys that have stable metal hydride phases. The sensor and/or switch response times make it quite suitable for measuring the concentration of hydrogen in a flowing gas ... | 03/06/2007 |
| 7184293 | Crosspoint-type ferroelectric memory A crosspoint-type ferroelectric memory is provided. In the crosspoint-type ferroelectric memory, a first memory cell array and a second memory cell array are stacked with a first interlayer insulating layer and a second interlayer insulating layer therebetween. The ... | 02/27/2007 |
| 7179704 | Methods of forming capacitors with high dielectric layers and capacitors so formed Methods of forming a capacitor of a semiconductor device can include forming a lower electrode of a capacitor on a semiconductor substrate and forming a dielectric material layer of Ba(Ti1-xSnx)O3 (BTS) or Ba(Ti1-xZrx... | 02/20/2007 |
| 7176553 | Integrated resistive elements with silicidation protection In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity... | 02/13/2007 |
| 7158219 | SERS-active structures including nanowires A SERS-active structure is disclosed that includes a substrate and at least one nanowire disposed on the substrate. The at least one nanowire includes a core including a first material and a coating including a SERS-active material. A SERS system is also disclosed t... | 01/02/2007 |
| 7141438 | Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower ele... | 11/28/2006 |
| 7115971 | Nanowire varactor diode and methods of making same A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate... | 10/03/2006 |
| 7115999 | Semiconductor device and method of manufacturing the same A semiconductor device has an active element structure formed on a semiconductor substrate. The active element has a connection region formed on a surface of the semiconductor substrate. An insulating film is formed on the semiconductor substrate. A connection hole ... | 10/03/2006 |
