Class 438/199 - Complementary insulated gate field effect transistors (i.e., CMOS)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making plural insulated gate field effect transistors
No. of patents: 1579
Last issue date: 05/22/2012

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8183104	Method for dual-channel nanowire FET device An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor includes a first group of nanowires made of silicon. The nanowire FET d...	05/22/2012
8183105	Integrated circuit device with stress reduction layer An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a redu...	05/22/2012
8178402	End functionalization of carbon nanotubes Carbon nanotubes may be selectively opened and their exposed ends functionalized. Opposite ends of carbon nanotubes may be functionalized in different fashions to facilitate self-assembly and other applications. ...	05/15/2012
8178401	Method for fabricating dual-metal gate device A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited ...	05/15/2012
8173499	Method of fabricating a gate stack integration of complementary MOS device A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal...	05/08/2012
8168489	High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ...	05/01/2012
8168491	Method for fabricating dual poly gate in semiconductor device A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and a second region; implanting first and second conductive type impurit...	05/01/2012
8168490	Co-packaging approach for power converters based on planar devices, structure and method A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can...	05/01/2012
8163607	Semiconductor device and method of making the same In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the Nix	04/24/2012
8158473	Method for manufacturing a semiconductor device having a silicide region comprised of a silicide of a nickel alloy To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer...	04/17/2012
8148221	Double anneal with improved reliability for dual contact etch stop liner scheme A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and...	04/03/2012
8138038	Superior fill conditions in a replacement gate approach by performing a polishing process based on a sacrificial fill material In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive material...	03/20/2012
8138036	Through silicon via and method of fabricating same A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, ...	03/20/2012
8138037	Method and structure for gate height scaling with high-k/metal gate technology A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate me...	03/20/2012
8133777	Method of fabricating memory A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of gates each having spacers is formed on the substrate. A plurality of openings is formed between the gates in the memory region. A f...	03/13/2012
RE43229	Method for manufacturing semiconductor device, including multiple heat treatment A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer...	03/06/2012
8119474	High performance capacitors in planar back gates CMOS A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first pl...	02/21/2012
8119472	Silicon device on Si:C SOI and SiGe and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat...	02/21/2012
8119473	High temperature anneal for aluminum surface protection The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate...	02/21/2012
8114728	Integration scheme for an NMOS metal gate A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate...	02/14/2012
8114727	Disposable spacer integration with stress memorization technique and silicon-germanium An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (	02/14/2012
8110459	MOSFET having a channel region with enhanced stress and method of forming same A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure...	02/07/2012
8105891	Method for tuning a work function of high-K metal gate devices A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within t...	01/31/2012
8101476	Stress memorization dielectric optimized for NMOS and PMOS A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not...	01/24/2012
8093121	ESD protection transistor An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting...	01/10/2012
8093119	CMOS microelectromechanical system (MEMS) device and fabrication method thereof A method for fabricating the MEMS device includes providing a substrate. Then, a structural dielectric layer is formed over the substrate at a first side, wherein a diaphragm is embedded in the structural dielectric layer. The substrate is patterned from a second si...	01/10/2012
8093120	Integrating a first contact structure in a gate last process A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming th...	01/10/2012
8080453	Gate stack having nitride layer A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a P+ region and an N+...	12/20/2011
8080454	Method of fabricating CMOS transistor A method of fabricating a CMOS transistor includes forming strained channels by re-crystallized amorphous polysilicon with the tensile film or the compressive film during annealing. C or Ge ions are optionally used to form solid-phase epitaxy to amplify the stress i...	12/20/2011
8071435	Manufacture of semiconductor device with stress structure A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristic...	12/06/2011
8062941	ESD protection transistor An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting...	11/22/2011
8058120	Integration scheme for strained source/drain CMOS using oxide hard mask A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate...	11/15/2011
8058119	Device scheme of HKMG gate-last process The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer;...	11/15/2011
8053301	CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions. ...	11/08/2011
8053300	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f...	11/08/2011
8048732	Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage cu...	11/01/2011
8048733	Method for fabricating a gate structure An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielect...	11/01/2011
8039335	Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may b...	10/18/2011
8034678	Complementary metal oxide semiconductor device fabrication method According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device, the method including: forming a first region and a second region in a substrate; forming the high-permittivity insulating film on the substrate in the...	10/11/2011
8034679	Fabrication of field-effect transistor having hypoabrupt body dopant distribution below source/drain zone An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt...	10/11/2011

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Did You Know...

PatentStorm News

Class 438/199 - Complementary insulated gate field effect transistors (i.e., CMOS)