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| Number | Title | Issue Date |
| 8138035 | Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bon... | 03/20/2012 |
| 8097501 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device, includes: forming a first-conductivity-type semiconductor region on a semiconductor layer; forming a mask member on the first-conductivity-type semiconductor region; selectively forming an opening in the mask member... | 01/17/2012 |
| 8039334 | Shared gate for conventional planar device and horizontal CNT A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one hor... | 10/18/2011 |
| 8039333 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorph... | 10/18/2011 |
| 8030148 | Structured strained substrate for forming strained transistors with reduced thickness of active layer In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of tran... | 10/04/2011 |
| 8012819 | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface... | 09/06/2011 |
| 7993995 | Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide laye... | 08/09/2011 |
| 7943451 | Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cel... | 05/17/2011 |
| 7897447 | Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase epitaxy (SPE) in the fabrication of nano-scale CMOS transistors using direct silicon bond substrate (DSB) and hybrid orientation technology (HOT) A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an anneal and an exposure to hydrochloric acid. The anneal and acid exposure can be performed within an epitax... | 03/01/2011 |
| 7892905 | Formation of strained Si channel and SiGesource/drain structures using laser annealing A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-ge... | 02/22/2011 |
| 7871876 | Method of forming a dual-plane complementary metal oxide semiconductor Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin reg... | 01/18/2011 |
| 7855111 | Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be suffi... | 12/21/2010 |
| 7833854 | Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present inv... | 11/16/2010 |
| 7811874 | Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carb... | 10/12/2010 |
| 7776674 | Hybrid strained orientated substrates and devices A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor mat... | 08/17/2010 |
| 7772059 | Method for fabricating graphene transistors on a silicon or SOI substrate A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an upper silicon layer mesa island, carbonizing the silicon layer into SiC utilizing a gaseous source, convert... | 08/10/2010 |
| 7767510 | Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed ove... | 08/03/2010 |
| 7749829 | Step height reduction between SOI and EPI for DSO and BOS integration A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS... | 07/06/2010 |
| 7745276 | Method for manufacturing SiC semiconductor device A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base reg... | 06/29/2010 |
| 7687340 | Protect diodes for hybrid-orientation substrate structures A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor re... | 03/30/2010 |
| 7674667 | CMOS structure including topographic active region A CMOS structure includes a first device located using a first active region within a semiconductor substrate, where the first active region is planar and has a first crystallographic orientation. The CMOS structure also includes a second device that is located usin... | 03/09/2010 |
| 7674668 | Method of manufacturing a semiconductor device After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidew... | 03/09/2010 |
| 7648868 | Metal-gated MOSFET devices having scaled gate stack thickness Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide laye... | 01/19/2010 |
| 7632728 | Method of forming TaC gate electrodes with crystal orientation ratio defining the work function A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111... | 12/15/2009 |
| 7625790 | FinFET with sublithographic fin width At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semicond... | 12/01/2009 |
| 7611937 | High performance transistors with hybrid crystal orientations A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semicon... | 11/03/2009 |
| 7595232 | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at leas... | 09/29/2009 |
| 7566604 | Method of fabricating a dual-gate structure that prevents cut-through and lowered mobility A method of fabricating a dual-gate semiconductor device, including forming a first PMOS transistor on a semiconductor substrate, the first PMOS transistor having a first gate electrode and a first gate insulation layer; and forming a first NMOS transistor on the se... | 07/28/2009 |
| 7534676 | Method of forming enhanced device via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 05/19/2009 |
| 7498216 | Method of forming high-performance CMOS SOI devices on hybrid crystal-oriented substrates Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors a... | 03/03/2009 |
| 7494858 | Transistor with improved tip profile and method of manufacture thereof Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of sh... | 02/24/2009 |
| 7462525 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein ... | 12/09/2008 |
| 7442596 | Methods of manufacturing fin type field effect transistors A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and i... | 10/28/2008 |
| 7439109 | Method of forming an integrated circuit structure on a hybrid crystal oriented substrate Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-typ... | 10/21/2008 |
| 7439108 | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region ... | 10/21/2008 |
| 7432570 | Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111... | 10/07/2008 |
| 7432149 | CMOS on SOI substrates with hybrid crystal orientations Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming ... | 10/07/2008 |
| 7425483 | Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present inv... | 09/16/2008 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 09/09/2008 |
| 7416967 | Semiconductor device, and method for manufacturing the same According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate in... | 08/26/2008 |
