Class 438/197 - Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a field effect transistor wherein the
No. of patents: 1913
Last issue date: 05/15/2012

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Number	Title	Issue Date
8178400	Replacement spacer for tunnel FETs A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy...	05/15/2012
8168488	Systems and methods for reducing contact to gate shorts A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the...	05/01/2012
8158472	Structures of SRAM bit cells A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to...	04/17/2012
8148220	Tunnel effect transistors based on elongate monocrystalline nanostructures having a heterostructure Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To ac...	04/03/2012
8143119	Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation region. The three transistors are of the same conductive type, and the first transistor and the second transisto...	03/27/2012
8133776	Semiconductor device and fabrication method for the same A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxG...	03/13/2012
8124467	Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors In sophisticated P-channel transistors, a high germanium concentration may be used in a silicon/germanium alloy, wherein an additional semiconductor cap layer may provide enhanced process conditions during the formation of a metal silicide. For example, a silicon la...	02/28/2012
8124466	Process for manufacturing voltage-controlled transistor The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boun...	02/28/2012
8114726	AlGaN/GaN HEMT with normally-off threshold minimized and method of manufacturing the same In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall form...	02/14/2012
8110457	Method of manufacturing semiconductor device To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n+-type semiconductor region, and a p+-type semiconductor region for a source or d...	02/07/2012
8110458	Fabrication of germanium nanowire transistors In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through...	02/07/2012
8105890	Method of forming a semiconductor structure A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then ...	01/31/2012
8101475	Field effect transistor and method for manufacturing the same A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A c...	01/24/2012
8097500	Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating a...	01/17/2012
8084312	Nitrogen based implants for defect reduction in strained silicon A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating charact...	12/27/2011
8076191	Method for manufacturing a semiconductor device including memory cell formation region In processing memory cells for forming a nonvolatile memory in a semiconductor device, a second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the sh...	12/13/2011
8076189	Method of forming a semiconductor device and semiconductor device A method of forming a semiconductor device comprises forming a control electrode over a portion of a semiconductor layer, forming recesses extending into the semiconductor layer on opposing sides of the control electrode, and forming doped regions in the semiconduct...	12/13/2011
8076190	Sea-of-fins structure on a semiconductor substrate and method of fabrication A semiconductor device and a method of fabricating a semiconductor device is disclosed, the method comprises including: forming etching an oxide layer to form a pattern of parallel oxide bars on a substrate; forming nitride spacers on side walls of the parallel oxid...	12/13/2011
8062940	Method of manufacturing semiconductor memory device, and semiconductor memory device A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell l...	11/22/2011
8058118	Methods of forming and operating back-side trap non-volatile memory cells Methods of forming and operating a back-side trap non-volatile memory cell. Method of forming a back-side trap non-volatile memory cell include forming a trapping material, forming two or more sub-layers of dielectric material on the trapping material, wherein a con...	11/15/2011
8053299	Method of fabrication of a FinFET element The present disclosure provides a FinFET element and method of fabricating a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, the method of fabrication the Ge-FinFET element inc...	11/08/2011
8039331	Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a sour...	10/18/2011
8039332	Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The c...	10/18/2011
8039330	Method for manufacturing semiconductor device The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer ...	10/18/2011
8034676	Semiconductor device and method of manufacturing the same A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the si...	10/11/2011
8034677	Integrated method for forming high-k metal gate FinFET devices Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such...	10/11/2011
8026133	Method of fabricating a semiconductor device with a non-uniform gate insulating film A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the ga...	09/27/2011
8021938	Semiconductor device and method for fabricating the same A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on a second region of the semiconductor substrate; and a second gate...	09/20/2011
8017465	Method for manufacturing array substrate of liquid crystal display A method for manufacturing an array substrate of liquid crystal display is performed with the following steps: providing a substrate having gate lines, a gate insulating layer and an active layer pattern formed thereon in this order; depositing a first transparent c...	09/13/2011
8017463	Expitaxial fabrication of fins for FinFET devices A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall. ...	09/13/2011
8017464	Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to plana...	09/13/2011
8012817	Transistor performance improving method with metal gate The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; for...	09/06/2011
8012818	Method for improving inversion layer mobility in a silicon carbide MOSFET A method of manufacturing a semiconductor device based on a SiC substrate involves forming an oxide layer on a Si-terminated face of the SiC substrate at an oxidation rate sufficiently high to achieve a near interface trap density below 5×1011 cm−...	09/06/2011
8003453	Self-aligned process for nanotube/nanowire FETs A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-al...	08/23/2011
8003454	CMOS process with optimized PMOS and NMOS transistor devices A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS de...	08/23/2011
7989280	Dielectric interface for group III-V semiconductor device A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region. ...	08/02/2011
7985638	Method of manufacturing semiconductor device A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewa...	07/26/2011
7985639	Method for fabricating a semiconductor device having a semiconductive resistor structure Methods are provided for fabricating a semiconductor device. A method forms a conductive fin arrangement on a first region of a semiconductor substrate. The method continues by forming a semiconductive resistor structure on a second region of the semiconductor subst...	07/26/2011
7977178	Asymmetric source/drain junctions for low power silicon on insulator devices A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor mater...	07/12/2011
7977177	Methods of forming nano-devices using nanostructures having self-assembly characteristics Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the self-assembly material layer, performing a surface treatment process ...	07/12/2011

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Class 438/197 - Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)