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| Number | Title | Issue Date |
| 7939393 | Method of adjusting FDSOI threshold voltage through oxide charges generation in the buried oxide Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconduct... | 05/10/2011 |
| 7915107 | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junc... | 03/29/2011 |
| 7883949 | Methods of forming silicon carbide switching devices including P-type channels Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defi... | 02/08/2011 |
| 7824973 | Method of forming a semiconductor device and semiconductor device thereof According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first wi... | 11/02/2010 |
| 7713804 | Method of forming an oxide isolated metal silicon-gate JFET A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, ga... | 05/11/2010 |
| 7709311 | JFET device with improved off-state leakage current and method of fabrication A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the firs... | 05/04/2010 |
| 7528026 | Method for reducing silicide defects by removing contaminants prior to drain/source activation By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process... | 05/05/2009 |
| 7411231 | JFET with drain and/or source modification implant The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would ot... | 08/12/2008 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri... | 03/11/2008 |
| 7341901 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 03/11/2008 |
| 7335988 | Use of palladium in IC manufacturing with conductive polymer bump An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The pr... | 02/26/2008 |
| 7329940 | Semiconductor structure and method of manufacture A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which in... | 02/12/2008 |
| 7312481 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio... | 12/25/2007 |
| 7297580 | Methods of fabricating transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer... | 11/20/2007 |
| 7271436 | Flash memory devices including a pass transistor Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor... | 09/18/2007 |
| 7265006 | Method of fabricating heterojunction devices integrated with CMOS A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may ... | 09/04/2007 |
| 7265039 | Method for fabricating semiconductor device with improved refresh time The present invention relates to a method for fabricating a semiconductor device with improved refresh time. The method includes the steps of: forming a plurality of gate lines on a substrate; forming a plurality of cell junctions by ion-implanting a first dopant wi... | 09/04/2007 |
| 7238987 | Lateral semiconductor device and method for producing the same A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce. The lateral semiconductor device comprises ... | 07/03/2007 |
| 7232729 | Method for manufacturing a double bitline implant The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep ... | 06/19/2007 |
| 7227203 | Power system inhibit method and device and structure therefor A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is d... | 06/05/2007 |
| 7226824 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 06/05/2007 |
| 7195968 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting threshold-adjusting ions under the select gate with the resist pattern ... | 03/27/2007 |
| 7176093 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 02/13/2007 |
| 7166506 | Poly open polish process A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with hi... | 01/23/2007 |
| 7161216 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the... | 01/09/2007 |
| 7144795 | Method for forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the... | 12/05/2006 |
| 7135363 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 11/14/2006 |
| 7135416 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device including a gallium nitride related semiconductor. The method include preparing a substrate having surface of a gallium nitride related semiconductor; contacting the surface with atomic nitrogen, which is obtained by ... | 11/14/2006 |
| 7126190 | Self-aligned gate and method A semiconductor structure includes a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by fir... | 10/24/2006 |
| 7122411 | SOI device with reduced drain induced barrier lowering A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and ... | 10/17/2006 |
| 7118948 | Semiconductor wafer having different impurity concentrations in respective regions A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an ou... | 10/10/2006 |
| 7089515 | Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For t... | 08/08/2006 |
| 7078347 | Method for forming MOS transistors with improved sidewall structures A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor ( | 07/18/2006 |
| 7071044 | Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of ... | 07/04/2006 |
| 7067362 | Integrated circuit with protected implantation profiles and method for the formation thereof A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the... | 06/27/2006 |
| 7067363 | Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel... | 06/27/2006 |
| 7060576 | Epitaxially deposited source/drain An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be d... | 06/13/2006 |
| 7045405 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 05/16/2006 |
| 7022560 | Method to manufacture high voltage MOS transistor by ion implantation A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain region (45), and a channel region (31), the channel having a short length and becoming well ali... | 04/04/2006 |
| 7011998 | High voltage transistor scaling tilt ion implant method The present invention is a high voltage transistor formation method and system that includes a varying or gradient concentration lightly doped drain and source implant region. The lightly doped drain (LDD) implant region has gradient concentration characteristics th... | 03/14/2006 |
