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| Number | Title | Issue Date |
| 8119471 | Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device including a vertical double-diffusedmetal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting ... | 02/21/2012 |
| 7763506 | Method for making an integrated circuit including vertical junction field effect transistors A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is... | 07/27/2010 |
| 7682889 | Trench field effect transistor and method of making it A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the tren... | 03/23/2010 |
| 7510924 | Method for manufacturing memory cell The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together def... | 03/31/2009 |
| 7432134 | Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme... | 10/07/2008 |
| 7372087 | Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration o... | 05/13/2008 |
| 7355244 | Electrical devices with multi-walled recesses The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell th... | 04/08/2008 |
| 7297580 | Methods of fabricating transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer... | 11/20/2007 |
| 7273771 | Common MOSFET process for plural devices A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusio... | 09/25/2007 |
| 7259048 | Vertical replacement-gate silicon-on-insulator transistor An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin s... | 08/21/2007 |
| 7256082 | Production method for semiconductor device A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a sil... | 08/14/2007 |
| 7256421 | Display device having a structure for preventing the deterioration of a light emitting device A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements' (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal lay... | 08/14/2007 |
| 7244970 | Low capacitance two-terminal barrier controlled TVS diodes A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and... | 07/17/2007 |
| 7242057 | Vertical transistor structures having vertical-surrounding-gates with self-aligned features The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silico... | 07/10/2007 |
| 7214627 | Graded junction termination extensions for electronic devices A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconducto... | 05/08/2007 |
| 7186599 | Narrow-body damascene tri-gate FinFET A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a ... | 03/06/2007 |
| 7187021 | Static induction transistor A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative cha... | 03/06/2007 |
| 7148526 | Germanium MOSFET devices and methods for making same A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side.... | 12/12/2006 |
| 7135362 | Isolation layer for CMOS image sensor and fabrication method thereof The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor. The isolation layer includes: a field insulating layer formed on a p... | 11/14/2006 |
| 7129179 | Method for topographical patterning of a device The device of the present invention facilitates engaging mating elements, such as actuators used in disc drives, with a pattern on the device. The improved device includes arcuate edges between at least one of the sidewalls in the pattern and the surface of the devi... | 10/31/2006 |
| 7109516 | Strained-semiconductor-on-insulator finFET device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... | 09/19/2006 |
| 7094637 | Method for minimizing the vapor deposition of tungsten oxide during the selective side wall oxidation of tungsten-silicon gates During a selective oxidation of gate structures that includes a polycrystalline silicon layer and a tungsten layer, which is known per se, a vapor deposition of tungsten oxide is prevented or at least greatly reduced by a special process. The gate structure is acted... | 08/22/2006 |
| 7067363 | Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel... | 06/27/2006 |
| 7053447 | Charge-trapping semiconductor memory device Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to fir... | 05/30/2006 |
| 7033877 | Vertical replacement-gate junction field-effect transistor An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of d... | 04/25/2006 |
| 7033876 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 04/25/2006 |
| 7019342 | Double-gated transistor circuit An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An in... | 03/28/2006 |
| 7015547 | Multi-configurable independently multi-gated MOSFET A double-gated transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First a... | 03/21/2006 |
| 7005696 | Structure of nonvolatile memory array A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of... | 02/28/2006 |
| 6995053 | Vertical thin film transistor A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate;... | 02/07/2006 |
| 6995052 | Method and structure for double dose gate in a JFET A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed af... | 02/07/2006 |
| 6967175 | Damascene gate semiconductor processing with local thinning of channel region A method of manufacturing a semiconductor device may include forming a fin on an insulator and forming a gate oxide on sides of the fin. The method may also include forming a gate structure over the fin and the gate oxide and forming a dielectric layer adjacent the ... | 11/22/2005 |
| 6962839 | Apparatus and manufacturing process of carbon nanotube gate field effect transistor The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intri... | 11/08/2005 |
| 6936522 | Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into ... | 08/30/2005 |
| 6933186 | Method for BEOL resistor tolerance improvement using anodic oxidation A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region... | 08/23/2005 |
| 6929988 | Method of making an ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. C... | 08/16/2005 |
| 6924207 | Method of fabricating a metal-insulator-metal capacitor A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interc... | 08/02/2005 |
| 6921963 | Narrow fin FinFET A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel. ... | 07/26/2005 |
| 6919647 | SRAM cell A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channe... | 07/19/2005 |
| 6919241 | Superjunction device and process for its manufacture A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward ... | 07/19/2005 |
