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| Number | Title | Issue Date |
| 8138034 | Flexible electret transducer assembly, speaker, and method for fabricating flexible electret transducer assembly A flexible electret transducer assembly including an electrical backplate and a membrane made of an electret material is disclosed. A plurality of spacers is formed on a surface of the electrical backplate in a longitudinal or latitudinal direction, and the spacers ... | 03/20/2012 |
| 7955918 | Robust transistors with fluorine treatment A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabr... | 06/07/2011 |
| 7790536 | Dopant confinement in the delta doped layer using a dopant segregration barrier in quantum well structures A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108cm−2 to be formed. In an embodiment of the... | 09/07/2010 |
| 7560325 | Methods of making lateral junction field effect transistors using selective epitaxial growth Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the d... | 07/14/2009 |
| 7429504 | Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the p... | 09/30/2008 |
| 7416909 | Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme... | 08/26/2008 |
| 7348228 | Deep buried channel junction field effect transistor (DBCJFET) A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distanc... | 03/25/2008 |
| 7338826 | Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN b... | 03/04/2008 |
| 7332795 | Dielectric passivation for semiconductor devices A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier lay... | 02/19/2008 |
| 7321132 | Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The... | 01/22/2008 |
| 7303948 | Semiconductor device including MOSFET having band-engineered superlattice A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally... | 12/04/2007 |
| 7297589 | Transistor device and method A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the ... | 11/20/2007 |
| 7288457 | Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain r... | 10/30/2007 |
| 7279701 | Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plur... | 10/09/2007 |
| 7279699 | Integrated circuit comprising a waveguide having an energy band engineered superlattice An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stac... | 10/09/2007 |
| 7265006 | Method of fabricating heterojunction devices integrated with CMOS A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may ... | 09/04/2007 |
| 7265002 | Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of la... | 09/04/2007 |
| 7244958 | Integration of strained Ge into advanced CMOS technology A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial deposit... | 07/17/2007 |
| 7229902 | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and ... | 06/12/2007 |
| 7227174 | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying lay... | 06/05/2007 |
| 7202494 | FINFET including a superlattice A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of st... | 04/10/2007 |
| 7153763 | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at le... | 12/26/2006 |
| 7141465 | Method of manufacturing a semiconductor device having a channel layer, a first semiconductor layer and a second semiconductor layer with a conductive impurity region A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semi... | 11/28/2006 |
| 7123792 | Configurable aperiodic grating device The invention relates to the field of grating structures. The invention provides a longitudinal grating having an aperiodic structure, wherein the grating has a selected response characteristic and any repeated unit cell in the structure is significantly longer than... | 10/17/2006 |
| 7109100 | Semiconductor device and method for manufacturing semiconductor device To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer... | 09/19/2006 |
| 7109052 | Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice A method for making an integrated circuit may include forming at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may... | 09/19/2006 |
| 7071119 | Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked grou... | 07/04/2006 |
| 7045404 | Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions a... | 05/16/2006 |
| 7045813 | Semiconductor device including a superlattice with regions defining a semiconductor junction A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying lay... | 05/16/2006 |
| 7045377 | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and ... | 05/16/2006 |
| 7037770 | Method of manufacturing strained dislocation-free channels for CMOS A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C l... | 05/02/2006 |
| 7038248 | Diverse band gap energy level semiconductor device Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof. ... | 05/02/2006 |
| 7034329 | Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked grou... | 04/25/2006 |
| 7033437 | Method for making semiconductor device including band-engineered superlattice A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direc... | 04/25/2006 |
| 7018900 | Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may be formed by forming a superlattice channel including a plural... | 03/28/2006 |
| 7015518 | HEMT device with a mesa isolating multilayer film To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor d... | 03/21/2006 |
| 7011997 | Method of fabricating a HEMT device To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor d... | 03/14/2006 |
| 7012287 | HEMT device with a mesa isolating multilayer film To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor d... | 03/14/2006 |
| 6993222 | Optical filter device with aperiodically arranged grating elements A method for producing aperiodic gratings and waveguides with aperiodic gratings uses a simulated annealing process that starts with a random configuration of grating elements and iteratively computes a spectral response from a Fourier transform of the configuration... | 01/31/2006 |
| 6974735 | Dual layer Semiconductor Devices A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer s... | 12/13/2005 |
