Bizarre Patents
Pillow with retractable umbrella
A pillow assembly having a supporting assembly and a retractable umbrella assembly that is easily transportable and allows a user to support his/her head while covering their face from sunlight.
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| Number | Title | Issue Date |
| 8173452 | Method to form a device by constructing a support element on a thin semiconductor lamina A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating... | 05/08/2012 |
| 8153453 | Betavoltaic battery with a shallow junction and a method for making same This is a novel SiC betavoltaic device (as an example) which comprises one or more “ultra shallow” P+N− SiC junctions and a pillared or planar device surface (as an example). Junctions are deemed “ultra shallow”, since the thin junction layer (w... | 04/10/2012 |
| 8133747 | Textured rear electrode structure for use in photovoltaic device such as CIGS/CIS solar cell A photovoltaic device including a rear electrode which may also function as a rear reflector. In certain example embodiments, the rear electrode comprises a reflective film (e.g., of Mo or the like) including one or more layers provided on an interior surface of a r... | 03/13/2012 |
| 8101437 | Method of forming three-terminal solar cell array A method for manufacturing three-terminal solar cell array is provided. In this method, only four major scribing or etching steps are needed to expose the three conductive layers of the three-terminal solar cell and isolate the individual solar cells. ... | 01/24/2012 |
| 8093075 | Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconduc... | 01/10/2012 |
| 8084280 | Method of manufacturing a solar cell using a pre-cleaning step that contributes to homogeneous texture morphology A method of manufacturing a solar cell wherein a pre-cleaning step is completed prior to a saw damage removal step and prior to texturization, thereby resulting in the subsequently formed textured surface to have a more homogeneous textural morphology. In one aspect... | 12/27/2011 |
| 8034642 | Method for pretreating electrochemical capacitor negative electrode, method for manufacturing the electrochemical capacitor negative electrode, and method for manufacturing electrochemical capacitor using the method for manufacturing the electrochemical capacitor negative electrode A negative electrode of an electrochemical capacitor includes an electrode layer using a material capable of reversibly absorbing and releasing a lithium ion. A method for pretreating the negative electrode includes forming a lithium layer on a substrate by a gas ph... | 10/11/2011 |
| 8017412 | Betavoltaic battery with a shallow junction and a method for making same This is a novel SiC betavoltaic device (as an example) which comprises one or more “ultra shallow” P+N− SiC junctions and a pillared or planar device surface (as an example). Junctions are deemed “ultra shallow”, since the thin junction layer (w... | 09/13/2011 |
| 7846750 | Textured rear electrode structure for use in photovoltaic device such as CIGS/CIS solar cell A photovoltaic device including a rear electrode which may also function as a rear reflector. In certain example embodiments, the rear electrode comprises a reflective film (e.g., of Mo or the like) including one or more layers provided on an interior surface of a r... | 12/07/2010 |
| 7833808 | Methods for forming multiple-layer electrode structures for silicon photovoltaic cells Methods for forming a photovoltaic cell electrode structure, wherein the photovoltaic cell includes a semiconductor substrate having a passivation layer thereon, includes providing a plurality of contact openings through the passivation layer to the semiconductor su... | 11/16/2010 |
| 7820460 | Patterned assembly for manufacturing a solar cell and a method thereof Apparatuses and methods for manufacturing a solar cell are disclosed. In a particular embodiment, the solar cell may be manufactured by disposing a solar cell in a chamber having a particle source; disposing a patterned assembly comprising an aperture and an assembl... | 10/26/2010 |
| 7517709 | Method of forming backside point contact structures for silicon solar cells A method for fabricating point contacts to the rear surface of a silicon solar cell by coating the rear surface with a masking layer and a laser absorptive layer and directing laser radiation to the rear surface to form openings therein after which doping material i... | 04/14/2009 |
| RE40137 | Methods for forming integrated circuits within substrates The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a substrate comprising: a) providing a recess in a substrate; b) printing ... | 03/04/2008 |
| 7332363 | Integrated battery pack with lead frame connection An integrated battery package, that contains semiconductor chips, for example to control and regulate battery charging and to monitor the package operation, uses a single lead frame to interconnect several internal chips, to internally connect said control chips to ... | 02/19/2008 |
| 7266988 | Resettable latching MEMS shock sensor apparatus and method The Resettable Latching MEMS Shock Sensor provides the capability of recording external shock extremes without consuming electrical power. The device incorporates a shock sensitive suspended proof mass, spring-loaded contacts, latches, and actuators for device reset... | 09/11/2007 |
| 7230321 | Integrated circuit package with laminated power cell having coplanar electrode An electrode that includes an electrically conductive, substantially planar body having a first thickness and a junction area, wherein the junction area is configured to receive a solid state power cell having a second thickness. The electrode also includes an arcua... | 06/12/2007 |
| 7227803 | Apparatus for reducing data corruption in a non-volatile memory The loss of data and/or the corruption of data that may occur in flash memory when a reset signal is received during a memory write cycle is prevented by delaying reset signals sent to the flash memory for a time period sufficient for a write cycle to be completed. ... | 06/05/2007 |
| 7217582 | Method for non-damaging charge injection and a system thereof A method and system for injecting charge includes providing a first material on a second material and injecting charge into the first material to trap charge at an interface between the first and second materials. The thickness of the first material is greater than ... | 05/15/2007 |
| 7211923 | Rotational motion based, electrostatic power source and methods thereof A power system includes a member with two or more sections and at least one pair of electrodes. Each of the two or more sections has a stored static charge. Each of the pair of electrodes is spaced from and on substantially opposing sides of the member from the othe... | 05/01/2007 |
| 7205165 | Method for determining the reliability of dielectric layers The present invention is generally directed to various methods for determining the reliability of dielectric layers. In one illustrative embodiment, the method comprises providing a device having a dielectric layer, applying a plurality of constant voltage pulses to... | 04/17/2007 |
| 7189642 | Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness of angstroms and a low temperature for semiconductor components In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewall... | 03/13/2007 |
| 7183633 | Optical cross-connect system An optical cross-connect switch comprises a base (216), a flap (211) and one or more electrically conductive landing pads (222) connected to the flap (211). The flap (211) has a bottom portion that is movably coupled to the base ( | 02/27/2007 |
| 7176543 | Method of eliminating curl for devices on thin flexible substrates, and devices made thereby A thin film semiconductor device such as a photovoltaic device is fabricated on a lightweight substrate material which is affixed to a layer of material which is in turn supported by a carrier. Following the fabrication of the device, the carrier is removed such as ... | 02/13/2007 |
| 7160741 | Planar voltage contrast test structure and method An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned... | 01/09/2007 |
| 7138284 | Method and apparatus for performing whole wafer burn-in A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of t... | 11/21/2006 |
| 7125730 | Power supply, a semiconductor making apparatus and a semiconductor wafer fabricating method using the same In power supply and a semiconductor making apparatus and a semiconductor fabricating method using the same, an abnormality can be detected when an offset occurs in a part constituting a closed-loop system of high-frequency power supply or dc power supply for a semic... | 10/24/2006 |
| 7076375 | Apparatus and method for incorporating the use of a processing device into a battery charger and tester A method and apparatus for charging and testing a battery wherein the battery is monitored throughout the process and loads are adjusted by a microprocessor based upon the data collected during the process. Furthermore, the microprocessor allows battery information ... | 07/11/2006 |
| 7045372 | Apparatus and method for forming a battery in an integrated circuit A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic... | 05/16/2006 |
| 7023097 | FBGA arrangement The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via w... | 04/04/2006 |
| 7013054 | Waveguides for performing spectroscopy with confined effective observation volumes The present invention is directed to a method and an apparatus for analysis of an analyte. The method involves providing a zero-mode waveguide which includes a cladding surrounding a core where the cladding is configured to preclude propagation of electromagnetic en... | 03/14/2006 |
| 7002215 | Floating entrance guard for preventing electrical short circuits Methods and apparatuses are provided for protecting an interconnect line in a microelectromechanical system. The interconnect line is disposed over a substrate for conducting electrical signals, such as from a bonding pad to a mechanical component to effect movement... | 02/21/2006 |
| 6961257 | Content addressable control system Pulse-width modulation (PWM) control and drive circuitry particularly applicable to an array of electrostatic actuators formed in a micro electromechanical system (MEMS), such as used for optical switching. The high-voltage portion may be incorporated in an integrat... | 11/01/2005 |
| 6897571 | Method for sawing wafers employing multiple indexing techniques for multiple die dimensions A semiconductor wafer saw and method of using the same for dicing semiconductor wafers including a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a ... | 05/24/2005 |
| 6833281 | On-chip substrate regulator test mode An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to oper... | 12/21/2004 |
| 6830940 | Method and apparatus for performing whole wafer burn-in A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of t... | 12/14/2004 |
| 6756242 | Method of modifying an integrated circuit The invention provides a method of modifying an integrated circuit, the method including the steps of selecting a scaling factor (72), scaling the circuit (74) according to the scaling factor, and adjusting the circuit for functionality and design rule... | 06/29/2004 |
| 6673657 | Kill index analysis for automatic defect classification in semiconductor wafers A kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. The method relates to... | 01/06/2004 |
| 6650000 | Apparatus and method for forming a battery in an integrated circuit A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of... | 11/18/2003 |
| 6608259 | Ground plane for a semiconductor chip AC-ground plane is for a semiconductor chip adapted to be mounted on a supporting member in a chip package, wherein said ground plane comprises at least one first capacitor plate provided within said chip, and at least one second capacitor plate provided ... | 08/19/2003 |
| 6514781 | Maintaining the state of a MEMS device in the event of a power failure A method and apparatus for maintaining the state of a MEMS device in the event of a power failure are disclosed. The apparatus and method may be used with a MEMS device generally having one or more MEMS elements moveably coupled to a substrate that uses e... | 02/04/2003 |
