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| Number | Title | Issue Date |
| 7883948 | Method and structure for reducing induced mechanical stresses Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the s... | 02/08/2011 |
| 7790535 | Depletion-free MOS using atomic-layer doping A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing l... | 09/07/2010 |
| 7781276 | Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is fo... | 08/24/2010 |
| 7772056 | Transistors for replacing metal-oxide semiconductor field-effect transistors in nanoelectronics Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down ... | 08/10/2010 |
| 7670890 | Silicide block isolated junction field effect transistor source, drain and gate An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated ... | 03/02/2010 |
| 7572689 | Method and structure for reducing induced mechanical stresses Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the s... | 08/11/2009 |
| 7365402 | LDMOS transistor An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial... | 04/29/2008 |
| 7329552 | Field effect transistor fabrication methods, field emission device fabrication methods, and field emission device operational methods The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a c... | 02/12/2008 |
| 7253492 | Semiconductor structure with via structure A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited... | 08/07/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7238577 | Method of manufacturing self-aligned n and p type stripes for a superjunction device A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alt... | 07/03/2007 |
| 7221034 | Semiconductor structure including vias A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited... | 05/22/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7202120 | Semiconductor integrated circuit device and fabrication process thereof A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation f... | 04/10/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7161544 | Mobile terminals including a built-in radio frequency test interface A radio frequency test interface for an electronic device includes a circuit board that includes a radio frequency contact. An antenna includes a resilient member that urges the antenna to engage the radio frequency contact. A test connector includes a conductive co... | 01/09/2007 |
| 7118952 | Method of making transistor with strained source/drain A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source regi... | 10/10/2006 |
| 7119399 | LDMOS transistor A semiconductor device has a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor with a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer... | 10/10/2006 |
| 7101744 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Porti... | 09/05/2006 |
| 7087473 | Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding ea... | 08/08/2006 |
| 7078296 | Self-aligned trench MOSFETs and methods for making the same Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOS... | 07/18/2006 |
| 7049669 | LDMOS transistor A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first conductivity type extending from a surface of the active region into the active region and substantially surroundin... | 05/23/2006 |
| 7033877 | Vertical replacement-gate junction field-effect transistor An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of d... | 04/25/2006 |
| 7021950 | System and method for preventing electric arcs in connectors feeding power loads and connector used A system and method for preventing electric arcs in connectors feeding power loads and connector used, Comprising several connectors (11) interspersed in an electric power distribution network, integrating first and second releasable socket coupling supports ... | 04/04/2006 |
| 6955965 | Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device Process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate; forming on the semiconductor substrate a bottom oxide layer; depositing on the bottom oxide layer a nitride layer, the deposited nitride ... | 10/18/2005 |
| 6949481 | Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device Process for fabricating a semiconductor device including steps of providing a semiconductor substrate having formed thereon a semiconductor device; depositing over the semiconductor device a spacer layer, the spacer layer having a first hydrogen content; and applyin... | 09/27/2005 |
| 6861303 | JFET structure for integrated circuit and fabrication method Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alte... | 03/01/2005 |
| 6812080 | Method of producing semiconductor device As shown in FIG. 1(a), a gate oxide film 12 is formed on an Si substrate 11. A polysilicon layer 13 is formed thereon. A natural oxide film 14 having an arbitrary thickness is formed on the polysilicon layer 13 after ... | 11/02/2004 |
| 6812077 | Method for patterning narrow gate lines Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line... | 11/02/2004 |
| 6803265 | Liner for semiconductor memories and manufacturing method therefor A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the... | 10/12/2004 |
| 6794232 | Method of making MOSFET gate electrodes with tuned work function Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impuri... | 09/21/2004 |
| 6787437 | Method of making a high-voltage transistor with buried conduction regions A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched th... | 09/07/2004 |
| 6759289 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first pluralit... | 07/06/2004 |
| 6734496 | Semiconductor device A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurali... | 05/11/2004 |
| 6724040 | Semiconductor device A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurali... | 04/20/2004 |
| 6613622 | Method of forming a semiconductor device and structure therefor A semiconductor device (10, 40) is formed to have a well (19) in a substrate (11). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance contact regions (26, 27) of a second conductivity type are form... | 09/02/2003 |
| 6509220 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to f... | 01/21/2003 |
| 6489190 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a fir... | 12/03/2002 |
| 6486011 | JFET structure and manufacture method for low on-resistance and low voltage application This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there ... | 11/26/2002 |
| 6468847 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a fir... | 10/22/2002 |
