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| Number | Title | Issue Date |
| 8053298 | Planar split-gate high-performance MOSFET structure and manufacturing method This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconduct... | 11/08/2011 |
| 8048731 | Method for reducing low frequency noise of transistor A method for reducing low frequency noise of a transistor operable at cryogenic temperatures includes a first step in which the transistor is illuminated with a light in a state that the transistor is activated and flowed current by supplying a power at a predetermi... | 11/01/2011 |
| 7968393 | Semiconductor device, design method and structure A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation regi... | 06/28/2011 |
| 7910417 | Distributed high voltage JFET A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average do... | 03/22/2011 |
| 7892904 | Amorphous silicon MONOS or MAS memory cell structure with OTP function A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlyi... | 02/22/2011 |
| 7795083 | Semiconductor structure and fabrication method thereof The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type... | 09/14/2010 |
| 7745273 | Semiconductor device and method for forming same A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semicond... | 06/29/2010 |
| 7736962 | Advanced JFET with reliable channel control and method of manufacture A junction field effect transistor comprises an insulating layer formed in a substrate. A source region of a first conductivity type is formed on the insulating layer, and a drain region of the first conductivity type is formed on the insulating layer and spaced apa... | 06/15/2010 |
| 7736961 | High voltage depletion FET employing a channel stopping implant A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop r... | 06/15/2010 |
| 7704813 | Reliable high-voltage junction field effect transistor and method of manufacturing therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio... | 04/27/2010 |
| 7687335 | Self aligned gate JFET structure and method A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second ... | 03/30/2010 |
| 7670889 | Structure and method for fabrication JFET in CMOS A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer... | 03/02/2010 |
| 7670888 | Low noise JFET Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in... | 03/02/2010 |
| 7615425 | Open source/drain junction field effect transistor The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experi... | 11/10/2009 |
| 7605031 | Semiconductor device having strain-inducing substrate and fabrication methods thereof A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from t... | 10/20/2009 |
| 7598132 | Active photosensitive structure with buried depletion layer An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. Du... | 10/06/2009 |
| 7556994 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power... | 07/07/2009 |
| 7544552 | Method for manufacturing junction semiconductor device A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first con... | 06/09/2009 |
| 7452763 | Method for a junction field effect transistor with reduced gate capacitance A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches t... | 11/18/2008 |
| 7442597 | Systems and methods that selectively modify liner induced stress The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing... | 10/28/2008 |
| 7416929 | Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device l... | 08/26/2008 |
| 7411231 | JFET with drain and/or source modification implant The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would ot... | 08/12/2008 |
| 7354052 | Suspension device In manufacturing a knuckle body forged or cast from light alloy of a suspension device, a large vertical height of a pair of bosses protruding downward from front and rear ends in a lower portion of the knuckle body may cause degradation in forgeability or castabili... | 04/08/2008 |
| 7348253 | High-quality SGOI by annealing near the alloy melting point A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant ... | 03/25/2008 |
| 7348228 | Deep buried channel junction field effect transistor (DBCJFET) A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distanc... | 03/25/2008 |
| 7335968 | High permeability composite films to reduce noise in high speed interconnects A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed ... | 02/26/2008 |
| 7327016 | High permeability composite films to reduce noise in high speed interconnects An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating ma... | 02/05/2008 |
| 7321132 | Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The... | 01/22/2008 |
| 7294859 | Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first condu... | 11/13/2007 |
| 7279707 | Test key structure A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each co... | 10/09/2007 |
| 7268378 | Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ... | 09/11/2007 |
| 7262461 | JFET and MESFET structures for low voltage, high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th... | 08/28/2007 |
| 7262099 | Methods of forming field effect transistors A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost port... | 08/28/2007 |
| 7253053 | Methods of forming transistor devices and capacitor constructions The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and ... | 08/07/2007 |
| 7241694 | Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a tre... | 07/10/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7235457 | High permeability layered films to reduce noise in high speed interconnects This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conduc... | 06/26/2007 |
| 7230434 | Multi-layered capacitor According to the present invention, a multi-layered capacitor includes a first capacitive element having a first conductor plate formed on a first layer, a second conductor plate formed on a second layer and an insulator arranged between the first and second conduct... | 06/12/2007 |
| 7226818 | High performance field effect transistors comprising carbon nanotubes fabricated using solution based processing The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have b... | 06/05/2007 |
| 7224016 | Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and... | 05/29/2007 |
