Class 438/185 - Multiple doping steps

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process including plural steps of doping the semiconductive
No. of patents: 54
Last issue date: 02/21/2012

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Number	Title	Issue Date
8119470	Mitigation of gate to contact capacitance in CMOS flow Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As suc...	02/21/2012
7932140	Semiconductor device and manufacturing method thereof A semiconductor device includes: a semiconductor substrate; a pair of first diffusion layer regions provided near a top face of the semiconductor substrate; a channel region provided between the first diffusion layer regions of the semiconductor substrate; a gate in...	04/26/2011
7301221	Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc...	11/27/2007
7297617	Method for controlling diffusion in semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc...	11/20/2007
7285449	Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electro...	10/23/2007
7238577	Method of manufacturing self-aligned n and p type stripes for a superjunction device A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alt...	07/03/2007
7208377	Silicon oxidation method A method for forming, by thermal oxidation, a silicon oxide layer on an integrated circuit including three-dimensional silicon patterns, includes implanting a first element according to a first angle with respect to a horizontal direction. The first element is elect...	04/24/2007
7183573	Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of ...	02/27/2007
7148158	Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film...	12/12/2006
7144776	Charge-trapping memory device An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and f...	12/05/2006
7063991	Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plu...	06/20/2006
7064017	Method of forming a CMOS transistor A method of forming a CMOS transistor on a substrate is provided, wherein the method requires only two implanting procedures to form all source/drain and light doped region. First, the source/drain of an NMOS transistor is formed by using a photoresist layer which c...	06/20/2006
7041541	Method for producing a semiconductor component, and semiconductor component produced by the same A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode. ...	05/09/2006
7005744	Conductor line stack having a top portion of a second layer that is smaller than the bottom portion A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over ...	02/28/2006
6967129	Semiconductor device and fabrication method thereof This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant ...	11/22/2005
6924180	Method of forming a pocket implant region after formation of composite insulator spacers A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconduc...	08/02/2005
6881616	System for forming a semiconductor device and method thereof including implanting through a L shaped spacer to form source and drain regions A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectr...	04/19/2005
6821830	Method for fabricating a semiconductor device including using a hard mask or a silylated photoresist for an angled tilted ion implant A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon g...	11/23/2004
6808966	Semiconductor device and fabrication method thereof This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant ...	10/26/2004
6777280	Method for fabricating an integrated circuit with a transistor electrode Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop ...	08/17/2004
6673645	Method and apparatus for a monolithic integrated mesfet and p-i-n optical receiver Disclosed is a semiconductor structure and manufacturing process for making an integrated FET and photodetector optical receiver on a semiconductor substrate. A FET is formed by forming at least one p channel in a p-well of the substrate and forming at le...	01/06/2004
6613621	Methods of forming self-aligned contact pads using a damascene gate process Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the ...	09/02/2003
6596554	Body-tied-to-source partially depleted SOI MOSFET A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node. A contact region of the same conductivity type as the body is formed in the source region with a m...	07/22/2003
6570233	Method of fabricating an integrated circuit The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor ...	05/27/2003
6482706	Method to scale down device dimension using spacer to confine buried drain implant A method of scaling down device dimension using spacer to confine the buried drain implant, applicable for forming memory device such as substrate/oxide/nitride/oxide/silicon (SONOS) stacked device or nitride read only memory (NROM) device. A patterned co...	11/19/2002
6426247	Low bitline capacitance structure and method of making same A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top diele...	07/30/2002
6406956	Poly resistor structure for damascene metal gate A layer of gate oxide and polysilicon are deposited over the surface of a substrate, these layers are etched to create a dummy gate and a resistor. Spacers are formed on the dummy gate and the resistor, suitable impurities are implanted self-aligned with ...	06/18/2002
6362117	Method of making integrated circuit with closely spaced components An integrated circuit (10, 60, 110, 210) is fabricated according to a method which includes the steps of providing a structure (12, 112, 212) having a top surface (13, 113, 213), and forming spaced first and second sections (16-18, 67-69, 72-73, 126-127, ...	03/26/2002
6300171	Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semicond...	10/09/2001
6251711	Method for forming bridge free silicide The proposed invention is a salicide process that is used to avoid bridge phenomena. In short, the proposed method for forming silicide without bridge phenomena comprises following steps: providing a substrate with a pad layer on the substrate; forming a ...	06/26/2001
6214654	Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget A method for making a ULSI MOSFET chip includes forming a sacrificial gate on a substrate along with activated source and drain regions, but without initially establishing a doped channel region. The polysilicon portion of the sacrificial gate is then rem...	04/10/2001
6153454	Convex device with selectively doped channel In manufacturing a transistor, a doping mask is formed above a substrate. The doping mask is constructed, so that a first region of the substrate for serving as a source in the transistor and a second region of the substrate for serving as a drain in the ...	11/28/2000
6020244	Channel dopant implantation with automatic compensation for variations in critical dimension An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentr...	02/01/2000
5953613	High performance MOSFET with a source removed from the semiconductor substrate and fabrication method thereof The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. ...	09/14/1999
5900662	MOS technology power device with low output resistance and low capacitance, and related manufacturing process A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resist...	05/04/1999
5837568	Manufacturing method of semiconductor devices To provide a manufacturing method of thin film transistors (TFT) using poly-silicone and having an LDD structure. In particular, the LDD sections of the TFTs are formed in an improved method so as to achieve a high throughput and stable performance of the...	11/17/1998
5585289	Method of producing metal semiconductor field effect transistor A field effect transistor includes a semi-insulating GaAs substrate; source, gate, and drain electrodes disposed on a surface of the GaAs substrate; a low carrier concentration active region disposed in the GaAs substrate lying beneath the gate electrode;...	12/17/1996
5504039	Method for making a self-aligned oxide gate cap A method for making a self-aligned oxide gate cap is provided. The method requires only one photoresist step to make a self-aligned oxide cap that can serve as an implant block and provide self-aligned contacts. A substrate with a gate line is provided. A...	04/02/1996
5471073	Field effect transistor and method for producing the field effect transistor In a field effect transistor including a Schottky gate electrode disposed on an active region in a compound semiconductor substrate, a compressive stress of the gate electrode and a tensile stress of an insulating film serving as a passivation are concent...	11/28/1995
5447874	Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish A method of manufacturing a semiconductor device gate is provided that reduces gate length variability while maintaining self-alignment and eliminating etch damage and substrate contamination. A gate opening (18) is formed in an oxide layer (16) using a a...	09/05/1995

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Class 438/185 - Multiple doping steps