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| Number | Title | Issue Date |
| 8114725 | Method of manufacturing MOS device having lightly doped drain structure The present invention discloses a method of manufacturing MOS device having a lightly doped drain (LDD) structure. The method includes: providing a first conductive type substrate; forming an isolation region in the substrate to define a device area; forming a gate ... | 02/14/2012 |
| 8110456 | Method for making a self aligning memory device A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An acces... | 02/07/2012 |
| 8048730 | Semiconductor device and method for manufacturing the same Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMO... | 11/01/2011 |
| 7718479 | Forming integrated circuits with replacement metal gate electrodes In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the ... | 05/18/2010 |
| 7682888 | Methods of forming NMOS/PMOS transistors with source/drains including strained materials A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbo... | 03/23/2010 |
| 7605030 | Hafnium tantalum oxynitride high-k dielectric and metal gates Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be f... | 10/20/2009 |
| 7517745 | Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate... | 04/14/2009 |
| 7510923 | Slim spacer implementation to improve drive current Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall space... | 03/31/2009 |
| 7510922 | Spacer T-gate structure for CoSiextendibility A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimensio... | 03/31/2009 |
| 7410891 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 08/12/2008 |
| 7405116 | Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selectiv... | 07/29/2008 |
| 7399690 | Methods of fabricating semiconductor devices and structures thereof Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is d... | 07/15/2008 |
| 7381622 | Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer... | 06/03/2008 |
| 7348265 | Semiconductor device having a silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located ov... | 03/25/2008 |
| 7344932 | Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n... | 03/18/2008 |
| 7332400 | Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized ... | 02/19/2008 |
| 7306995 | Reduced hydrogen sidewall spacer oxide An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a sp... | 12/11/2007 |
| 7304330 | Nitride semiconductor device A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen... | 12/04/2007 |
| 7276408 | Reduction of dopant loss in a gate structure A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfac... | 10/02/2007 |
| 7276423 | III-nitride device and method with variable epitaxial growth direction A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the... | 10/02/2007 |
| 7259050 | Semiconductor device and method of making the same A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of th... | 08/21/2007 |
| 7256081 | Structure and method to induce strain in a semiconductor device channel with stressed film under the gate A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film su... | 08/14/2007 |
| 7255801 | Deep submicron CMOS compatible suspending inductor A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, crea... | 08/14/2007 |
| 7244642 | Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255 | 07/17/2007 |
| 7235861 | NPN transistor having reduced extrinsic base resistance and improved manufacturability A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may... | 06/26/2007 |
| 7225047 | Method, system and medium for controlling semiconductor wafer processes using critical dimension measurements Methods, systems, and mediums of controlling a semiconductor manufacturing process are described. The method comprises the steps of measuring at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, determin... | 05/29/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7217626 | Transistor fabrication methods using dual sidewall spacers Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is impla... | 05/15/2007 |
| 7198996 | Component built-in module and method for producing the same A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the cor... | 04/03/2007 |
| 7180090 | Method of forming thin-film transistor devices with electro-static discharge protection A silicon layer is formed on a substrate, and then the silicon layer is patterned, and source regions, drain regions and connectors, all with the same conductivity, are formed. The source regions are connected with the drain regions electrically by the connectors, a... | 02/20/2007 |
| 7170110 | Semiconductor device and method for fabricating the same A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT fi... | 01/30/2007 |
| 7169676 | Semiconductor devices and methods for forming the same including contacting gate to source Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped re... | 01/30/2007 |
| 7169677 | Method for producing a spacer structure A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering depo... | 01/30/2007 |
| 7157374 | Method for removing a cap from the gate of an embedded silicon germanium semiconductor device A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and ... | 01/02/2007 |
| 7157318 | Method of fabricating SRAM device A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on... | 01/02/2007 |
| 7151881 | Impurity-based waveguide detectors An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an op... | 12/19/2006 |
| 7148158 | Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film... | 12/12/2006 |
| 7138340 | Method for fabricating semiconductor device without damaging hard mask during contact formation process Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer... | 11/21/2006 |
| 7098098 | Methods for transistors formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a... | 08/29/2006 |
| 7094694 | Semiconductor device having MOS varactor and methods for fabricating the same In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in ... | 08/22/2006 |
