Class 438/183 - Dummy gate

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process wherein a temporary gate is formed or utilized at
No. of patents: 295
Last issue date: 05/01/2012

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Number	Title	Issue Date
8168487	Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewa...	05/01/2012
8093116	Method for N/P patterning in a gate last process A method is provided that includes providing a substrate, forming a first gate structure in a first region and a second gate structure in a second region, the first and second gate structures each including a high-k dielectric layer, a silicon layer, and a hard mask...	01/10/2012
8093117	Method of forming a metal gate The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an ope...	01/10/2012
8084311	Method of forming replacement metal gate with borderless contact and structure thereof Embodiments of the present invention provide a method of forming borderless contact for transistor in a replacement metal gate process. The method includes forming a gate on top of a substrate and forming spacers adjacent to sidewalls of the gate; lowering height of...	12/27/2011
8008143	Method to form a semiconductor device having gate dielectric layers of varying thicknesses A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in t...	08/30/2011
7955917	Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls an...	06/07/2011
7939392	Method for gate height control in a gate last process A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD)...	05/10/2011
7858457	Methods of forming integrated circuit devices including a depletion barrier layer at source/drain regions Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite si...	12/28/2010
7785946	Integrated circuits and methods of design and manufacture thereof Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes o...	08/31/2010
7759182	Dummy active area implementation Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy...	07/20/2010
7754552	Preventing silicide formation at the gate electrode in a replacement metal gate technology A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or e...	07/13/2010
7648867	Method for fabricating a semiconductor device A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to ...	01/19/2010
7645653	Method for manufacturing a semiconductor device having a polymetal gate electrode structure A process for manufacturing a semiconductor device having a polymetal structure includes patterning a bottom electrode layer by using a sacrificial layer pattern oxidizing the side surface of the patterned bottom electrode layer, forming a sidewall oxide film on bot...	01/12/2010
7601574	Methods for fabricating a stress enhanced MOS transistor Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electro...	10/13/2009
7585716	High-k/metal gate MOSFET with reduced parasitic capacitance The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semicond...	09/08/2009
7569443	Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-t...	08/04/2009
7528025	Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first...	05/05/2009
7488634	Method for fabricating flash memory device A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern...	02/10/2009
7462522	Method and structure for improving device performance variation in dual stress liner technology A method for making a semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, is provided. In accordance with embodiments of the present invention, the dual stress lin...	12/09/2008
7435636	Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls an...	10/14/2008
7425478	Semiconductor device and method of fabricating the same A semiconductor device and a method of fabricating the semiconductor device are described. There is provided the semiconductor device including, a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a two-step gate electrode formed on th...	09/16/2008
7422936	Facilitating removal of sacrificial layers via implantation to form replacement metal gates Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate...	09/09/2008
7405116	Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selectiv...	07/29/2008
7399675	Electronic device including an array and process for forming the same An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can ...	07/15/2008
7396730	Integrated circuit devices including an L-shaped depletion barrier layer adjacent opposite sides of a gate pattern and methods of forming the same Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite si...	07/08/2008
7371626	Method for maintaining topographical uniformity of a semiconductor memory array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer s...	05/13/2008
7368358	Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a...	05/06/2008
7364995	Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co...	04/29/2008
7361961	Method and apparatus with varying gate oxide thickness An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickn...	04/22/2008
7358122	High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l...	04/15/2008
7352036	Semiconductor power device having a top-side drain using a sinker trench A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extend...	04/01/2008
7344932	Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n...	03/18/2008
7342290	Semiconductor metal contamination reduction for ultra-thin gate dielectrics A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom ...	03/11/2008
7339262	Tape circuit substrate and semiconductor apparatus employing the same A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply vol...	03/04/2008
7335988	Use of palladium in IC manufacturing with conductive polymer bump An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The pr...	02/26/2008
7335562	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation...	02/26/2008
7332386	Methods of fabricating fin field transistors A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides ...	02/19/2008
7332433	Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t...	02/19/2008
7332421	Method of fabricating gate electrode of semiconductor device A method of forming a gate electrode of a semiconductor device includes forming a damascene pattern for fabricating a metal electrode on an upper part of a poly silicon gate so as to prevent a metal electrode from being oxidized when the poly silicon electrode and t...	02/19/2008
7329548	Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; ...	02/12/2008

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Class 438/183 - Dummy gate