Did You Know...
...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8105889 | Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a mask... | 01/31/2012 |
| 8080452 | Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one ... | 12/20/2011 |
| 7902013 | Method of forming a semiconductor die with reduced RF attenuation An electrically floating region is formed in the top surface of a semiconductor wafer to implement a radio frequency (RF) blocking structure. The RF blocking structure lies below the metal pads and traces that carry an RF signal in a metal interconnect structure to ... | 03/08/2011 |
| 7754551 | Method for making very low metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EO... | 07/13/2010 |
| 7727827 | Method of forming a semiconductor structure A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant i... | 06/01/2010 |
| 7645652 | CMOS image sensor and method for fabricating the same A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semiconductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transi... | 01/12/2010 |
| 7592212 | Methods for determining a dose of an impurity implanted in a semiconductor substrate Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion s... | 09/22/2009 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7361912 | Doping method, doping apparatus, and control system for doping apparatus A doping method capable of controlling a dose amount in response to a change the ratio in ion species during a doping process, a control system for controlling a doping amount, and a doping apparatus having a control system are provided. An ion current value of a sp... | 04/22/2008 |
| 7348227 | Semiconductor device and manufacturing method thereof A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a ... | 03/25/2008 |
| 7294859 | Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first condu... | 11/13/2007 |
| 7244642 | Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255 | 07/17/2007 |
| 7238577 | Method of manufacturing self-aligned n and p type stripes for a superjunction device A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alt... | 07/03/2007 |
| 7226824 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 06/05/2007 |
| 7198967 | Active matrix type semiconductor display device There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potent... | 04/03/2007 |
| 7192854 | Method of plasma doping A method of plasma doping in which dilution of B2H6 is maximized for enhanced safety and stable plasma generation and sustention can be carried out without lowering of doping efficiency and in which the amount of dopant injected can be easily c... | 03/20/2007 |
| 7160762 | Method for manufacturing semiconductor device, semiconductor device, and laser irradiation apparatus It is an object of the present invention to provide a laser irradiation apparatus being able to crystallize the semiconductor film homogeneously while suppressing the variation of the crystallinity in the semiconductor film and the unevenness of the state of the sur... | 01/09/2007 |
| 7157321 | Semiconductor device and method for manufacturing the same A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: fo... | 01/02/2007 |
| 7122408 | Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concent... | 10/17/2006 |
| 7112497 | Multi-layer reducible sidewall process The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors c... | 09/26/2006 |
| 7109100 | Semiconductor device and method for manufacturing semiconductor device To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer... | 09/19/2006 |
| 7063991 | Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plu... | 06/20/2006 |
| 6960498 | Doping method, doping apparatus, and control system for doping apparatus A doping method capable of controlling a dose amount in response to a change the ratio in ion species during a doping process, a control system for controlling a doping amount, and a doping apparatus having a control system are provided. An ion current value of a sp... | 11/01/2005 |
| 6953740 | Highly doped III-nitride semiconductors A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by firs... | 10/11/2005 |
| 6881616 | System for forming a semiconductor device and method thereof including implanting through a L shaped spacer to form source and drain regions A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectr... | 04/19/2005 |
| 6872604 | Method of fabricating a light emitting device There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manu... | 03/29/2005 |
| 6861320 | Method of making starting material for chip fabrication comprising a buried silicon nitride layer The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2 | 03/01/2005 |
| 6773972 | Memory cell with transistors having relatively high threshold voltages in response to selective gate doping A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor s... | 08/10/2004 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6613621 | Methods of forming self-aligned contact pads using a damascene gate process Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the ... | 09/02/2003 |
| 6593194 | Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate, and method of making the same A method for making a metal-insulator-semiconductor field effect transistor (MISFET) having an oxidized aluminum nitride gate insulator formed on a silicon or gallium nitride substrate. The method of making the MISFET comprises the steps of depositing an ... | 07/15/2003 |
| 6562671 | Semiconductor display device and manufacturing method thereof A semiconductor display device which comprises the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off... | 05/13/2003 |
| 6558995 | Holographic, laser-induced fabrication of indium nitride quantum wires and quantum dots A semiconductor device is constructed of at least one indium nitride or indium nitride alloy nanostructure on a substrate or other thing film layer. The method used to create the semiconductor device involves illuminating the substrate with a lateral inte... | 05/06/2003 |
| 6555844 | Semiconductor device with minimal short-channel effects and low bit-line resistance A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation ele... | 04/29/2003 |
| 6541319 | Method of manufacturing a self-aligned gate transistor with P-type impurities selectively implanted below the gate, source and drain electrodes The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channe... | 04/01/2003 |
| 6458640 | GaAs MESFET having LDD and non-uniform P-well doping profiles A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type regi... | 10/01/2002 |
| 6403410 | Plasma doping system and plasma doping method The present invention relates to a plasma doping system capable of handling larger-diameter wafers and of introducing impurities to a shallow depth with a lower energy level. The plasma doping system includes a plasma generation chamber provided with a hi... | 06/11/2002 |
| 6395573 | Laser diode and method for fabricating the same Provided with a laser diode and its fabricating method including the steps of: sequentially forming a first conductivity type clad layer, an active layer, a second conductivity type first clad layer, an etch stop layer, a second conductivity type second c... | 05/28/2002 |
| 6387738 | Method for manufacturing a thin film transistor There is provided a method for manufacturing a thin film transistor. The present invention can reduce the number of process steps for manufacturing a thin film transistor, and also can lower contact resistance between layers. The manufacturing method depo... | 05/14/2002 |
| 6323073 | Method for forming doped regions on an SOI device An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed... | 11/27/2001 |
