Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7659155 | Method of forming a transistor having gate and body in direct self-aligned contact A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the bod... | 02/09/2010 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7419892 | Semiconductor devices including implanted regions and protective layers and methods of forming the same Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, ... | 09/02/2008 |
| 7285806 | Semiconductor device having an active region formed from group III nitride The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor.... | 10/23/2007 |
| 7256113 | System for forming a semiconductor device and method thereof A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectr... | 08/14/2007 |
| 7247531 | Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Ano... | 07/24/2007 |
| 7227212 | Method of forming a floating metal structure in an integrated circuit In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is form... | 06/05/2007 |
| 7220646 | Integrated circuit structure with improved LDMOS design A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first ... | 05/22/2007 |
| 7195998 | Compound semiconductor device and manufacturing method thereof A compound semiconductor device including: an isolated mesa section on which an upper surface having two pairs of parallel sides is formed by mesa etching a compound semiconductor wafer, wherein the mesa section is formed from at least a forward mesa surface which i... | 03/27/2007 |
| 7183150 | Resist protect oxide structure of sub-micron salicide process In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet... | 02/27/2007 |
| 7176079 | Method of fabricating a semiconductor device with a wet oxidation with steam process A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrat... | 02/13/2007 |
| 7157775 | Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 01/02/2007 |
| 7157345 | Source side injection storage device and method therefor A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16)... | 01/02/2007 |
| 7141464 | Method of fabricating T-type gate Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the sec... | 11/28/2006 |
| 7138313 | Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, t... | 11/21/2006 |
| 7138318 | Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path of the ion imp... | 11/21/2006 |
| 7118965 | Methods of fabricating nonvolatile memory device A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an ac... | 10/10/2006 |
| 7101744 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Porti... | 09/05/2006 |
| 7022562 | Field-effect transistor with horizontal self-aligned gates and the production method therefor A field-effect transistor including: a support substrate, an active area forming a channel; a first active gate which is associated with a first face of the active area; source and drain areas which are formed in the active area and which are self-aligned on the fir... | 04/04/2006 |
| 6977425 | Semiconductor device having a lateral MOSFET and combined IC using the same A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and... | 12/20/2005 |
| 6967129 | Semiconductor device and fabrication method thereof This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant ... | 11/22/2005 |
| 6939768 | Method of forming self-aligned contacts A method of forming self-aligned contacts that includes providing at least one stacked-gate structure on a semiconductor substrate, forming a first dielectric layer on the stacked-gate structure and the semiconductor substrate, forming a second dielectric layer on t... | 09/06/2005 |
| 6924225 | Method for producing an electrically conductive contact An electrically conductive contact can be used to connect an integrated component to an interconnect. A sacrificial layer is deposited on a liner and planarized until a surface of the integrated component is uncovered. The sacrificial layer is patterned to define th... | 08/02/2005 |
| 6906389 | High-voltage, high-cutoff-frequency electronic MOS device An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a... | 06/14/2005 |
| 6872604 | Method of fabricating a light emitting device There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manu... | 03/29/2005 |
| 6849484 | Method of manufacturing semiconductor device As an opening exposing a surface of an element-forming region positioned in a region lying between two gate electrodes, a first opening is formed based on a resist pattern formed such that a portion of a region where the opening is formed overlaps two-dimensionally ... | 02/01/2005 |
| 6844225 | Self-aligned mask formed utilizing differential oxidation rates of materials A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe... | 01/18/2005 |
| 6815274 | Resist protect oxide structure of sub-micron salicide process In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet... | 11/09/2004 |
| 6808966 | Semiconductor device and fabrication method thereof This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant ... | 10/26/2004 |
| 6777278 | Methods of fabricating aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel laye... | 08/17/2004 |
| 6773970 | Method of producing a semiconductor device having improved gate structure A method of producing a semiconductor device able to prevent outward diffusion of an impurity from a gate electrode and improve the device quality, the method comprising the steps of forming a gate electrode made of a semiconductor layer on a substrate (preferably S... | 08/10/2004 |
| 6770531 | Adhesive material for programmable device In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an adhesive is formed on a dielectric and on an electrode, the adhesive is patterned exposing the electrode, and a program... | 08/03/2004 |
| 6689664 | Transistor fabrication method A transistor fabrication method comprises: sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate; etching the substrate to form a trench; sequentially forming a first oxide film within the trench and a cylindrical i... | 02/10/2004 |
| 6613621 | Methods of forming self-aligned contact pads using a damascene gate process Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the ... | 09/02/2003 |
| 6602759 | Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped p... | 08/05/2003 |
| 6596554 | Body-tied-to-source partially depleted SOI MOSFET A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node. A contact region of the same conductivity type as the body is formed in the source region with a m... | 07/22/2003 |
| 6469769 | Manufacturing method of a liquid crystal display It is intended to provide a manufacturing method of a liquid crystal display that can reduce the manufacturing cost by decreasing the number of masks. A gate insulating film, a semiconductor film, and a silicon nitride film are laid on a substrate on whic... | 10/22/2002 |
| 6448120 | Totally self-aligned transistor with tungsten gate A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to... | 09/10/2002 |
| 6440786 | Boron-carbide and boron rich rhobohedral based transistors and tunnel diodes The present invention relates to the fabrication of a boron carbide/boron semiconductor devices. The results suggest that with respect to the approximately 2 eV band gap pure boron material, 0.9 eV band gap boron carbide (B5 C) acts as a p-type... | 08/27/2002 |
| 6407434 | Hexagonal architecture Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by o... | 06/18/2002 |
