Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Number | Title | Issue Date |
| 8178368 | Test chiplets for devices A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection. ... | 05/15/2012 |
| 8114688 | Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective ... | 02/14/2012 |
| 8101436 | Dicing method, method of inspecting integrated circuit element, substrate holding device, and pressure sensitive adhesive film A dicing method, integrated circuit chip testing method, substrate holding apparatus, and adhesive film are disclosed. A first adhesive film 22 in which the adhesion is reduced by ultraviolet radiation is stretched inside a ring-like frame 21 larger th... | 01/24/2012 |
| 8097475 | Method of production of a contact structure A probe card having a plurality of silicon finger contactors contacting pads provided on a tested semiconductor wafer and a probe board mounting the plurality of silicon finger contactors on its surface, wherein each silicon finger contactor has a base part on which... | 01/17/2012 |
| 8071399 | Method of manufacturing a semiconductor integrated circuit device An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. Measures are: obtaining an image of a region P... | 12/06/2011 |
| 8039277 | Providing current control over wafer borne semiconductor devices using overlayer patterns Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through... | 10/18/2011 |
| 8021899 | Method of manufacturing a semiconductor device including optical test pattern above a light shielding film The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulatin... | 09/20/2011 |
| 7993942 | Method of detecting heavy metal in semiconductor substrate A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a metal/oxide film/semiconductor junction element by using a mercury probe met... | 08/09/2011 |
| 7989232 | Method of using electrical test structure for semiconductor trench depth monitor Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the ... | 08/02/2011 |
| 7973544 | Thermal monitoring and management of integrated circuits The invention, in one aspect, provides a semiconductor device (100), including transistors (105), dielectric layers (115, 120) located over the transistors (105), interconnects (122) formed within the dielectric layers (115, 120... | 07/05/2011 |
| 7939348 | E-beam inspection structure for leakage analysis A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined str... | 05/10/2011 |
| 7927895 | Varying capacitance voltage contrast structures to determine defect resistance A method for determining resistances of defects in a test structure, comprising: forming a first layer of the test structure having elements under test; generating a first e-beam image of the first layer, the first e-beam image graphically identifying defects detect... | 04/19/2011 |
| 7910385 | Method of fabricating microelectronic devices Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual... | 03/22/2011 |
| 7901958 | Fabrication method of semiconductor integrated circuit device To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via th... | 03/08/2011 |
| 7901957 | Disguising test pads in a semiconductor package A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such a... | 03/08/2011 |
| 7888143 | Apparatus and method for characterizing structures within an integrated circuit An apparatus and method of utilizing an electron beam and ion beam microscope in combination with nanomanipulators to improve the accuracy of the characterization of structures within an integrated circuit. Probes attached to the nanomanipulators, i.e., nano-probes,... | 02/15/2011 |
| 7867790 | Substrate of probe card and method for regenerating thereof Provided are a substrate of a probe card for installing a plurality of probes thereon to inspect an object by contacting the probes to the object, and a method for repairing the substrate. The substrate includes main channels electrically connected to the probes; an... | 01/11/2011 |
| 7858406 | Semiconductor device test structures and methods Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line ... | 12/28/2010 |
| 7855090 | In line test circuit and method for determining interconnect electrical properties and integrated circuit incorporating the same A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit inc... | 12/21/2010 |
| 7851237 | Semiconductor device test structures and methods Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test st... | 12/14/2010 |
| 7829357 | Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of mai... | 11/09/2010 |
| 7824935 | Methods of combinatorial processing for screening multiple samples on a semiconductor substrate In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for s... | 11/02/2010 |
| 7803644 | Across reticle variation modeling and related reticle Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the mea... | 09/28/2010 |
| 7781239 | Semiconductor device defect type determination method and structure A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure... | 08/24/2010 |
| 7776626 | Manufacturing method of semiconductor integrated circuit device A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic ... | 08/17/2010 |
| 7776627 | Flexible structures for interconnect reliability test A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of th... | 08/17/2010 |
| 7718448 | Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS tr... | 05/18/2010 |
| 7709279 | Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD protection, are provided. An ESD structure may be associated with each interconnect, either individually or sh... | 05/04/2010 |
| 7642106 | Methods for identifying an allowable process margin for integrated circuits A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality... | 01/05/2010 |
| 7608469 | Method of fabricating a chip A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of th... | 10/27/2009 |
| 7588950 | Test pattern for reliability measurement of copper interconnection line having moisture window and method for manufacturing the same Disclosed is a test pattern for a reliability measurement of a copper interconnection line having a moisture window and a method for manufacturing the same. The method includes the steps of: a first inter-layer insulation layer formed on the substrate; a plurality o... | 09/15/2009 |
| 7582494 | Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operatio... | 09/01/2009 |
| 7582493 | Distinguishing between dopant and line width variation components A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A c... | 09/01/2009 |
| 7560293 | Evaluation method using a TEG, a method of manufacturing a semiconductor device having the TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recording the program The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped r... | 07/14/2009 |
| 7550303 | Systems and methods for overlay shift determination Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe mem... | 06/23/2009 |
| 7534632 | Method for circuits inspection and method of the same A method for circuit inspection comprises steps of providing a substrate having a conductive line; and forming a metal layer on at least the conductive layer to increase a contrast between the conductive layer and adjacent area for the circuit inspection. The method... | 05/19/2009 |
| 7517708 | Real-time parameter tuning using wafer temperature The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination... | 04/14/2009 |
| 7473568 | Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inse... | 01/06/2009 |
| 7468283 | Method and resulting structure for fabricating test key structures in DRAM structures A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate an... | 12/23/2008 |
| 7442559 | Method for producing an optical or electronic module provided with a plastic package A method for producing an optical or electronic module provided with a plastic package including: providing at least one optical or electronic component, the component having an operative region, via which it is in operative connection with the surroundings in the f... | 10/28/2008 |
