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Class 438/177 - Closed or loop gate


Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a Schottky field effect transistor wherein
No. of patents: 12
Last issue date: 04/03/2012


NumberTitleIssue Date
8148219Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same
A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semico...
04/03/2012
7989279Method of fabricating semiconductor device
A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves...
08/02/2011
7439104Semiconductor device with increased channel length and method for fabricating the same
A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar acti...
10/21/2008
7435653Methods for forming a wrap-around gate field effect transistor
A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure...
10/14/2008
7338870Methods of fabricating semiconductor devices
Methods of recovering damage on a semiconductor device by performing a hydrogen annealing process are disclosed. An example disclosed method includes forming an STI structure on a semiconductor substrate; forming a gate electrode and spacers on the sidewalls of the ...
03/04/2008
7220636Process for controlling performance characteristics of a negative differential resistance (NDR) device
A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operation...
05/22/2007
6977185Printhead integrated circuit
An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the trans...
12/20/2005
6913958Method for patterning a feature using a trimmed hardmask
In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed ha...
07/05/2005
6849483Charge trapping device and method of forming the same
A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, an...
02/01/2005
6759286Method of fabricating a gate structure of a field effect transistor using a hard mask
A method of fabricating a gate structure of a field effect transistor, comprising forming a hard mask, etching a gate electrode, and contemporaneously forming a gate dielectric and removing the hard mask. ...
07/06/2004
5147812Fabrication method for a sub-micron geometry semiconductor device
A method for fabricating a sub-micron geometry semiconductor device using a chromeless mask. An optical exposure system (22) directs light through a chromeless mask (21). The chromeless mask (21) uses destructive interference of light to pattern a light s...
09/15/1992
4729966Process for manufacturing a Schottky FET device using metal sidewalls as gates
A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on t...
03/08/1988
 
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