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| Number | Title | Issue Date |
| 8158471 | Capacitorless DRAM on bulk silicon A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of... | 04/17/2012 |
| 8105888 | Diode assembly A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor l... | 01/31/2012 |
| 8093114 | Method for making split dual gate field effect transistor A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first pluralit... | 01/10/2012 |
| 7968392 | Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, a... | 06/28/2011 |
| 7915105 | Method for patterning a metal gate The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the firs... | 03/29/2011 |
| 7829399 | Capacitorless DRAM on bulk silicon A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of... | 11/09/2010 |
| 7807522 | Lanthanide series metal implant to control work function of metal gate electrodes Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric... | 10/05/2010 |
| 7659154 | Dual gate CMOS fabrication The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the ... | 02/09/2010 |
| 7582517 | Method for making split dual gate field effect transistor A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first pluralit... | 09/01/2009 |
| 7537985 | Double gate isolation A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a bur... | 05/26/2009 |
| 7528024 | Dual work function metal gate integration in semiconductor devices The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and ... | 05/05/2009 |
| 7517744 | Capacitorless DRAM on bulk silicon A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of... | 04/14/2009 |
| 7462521 | Dual-gate device and method A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of... | 12/09/2008 |
| 7432143 | Method for forming gate of semiconductor device There is provided a method for forming a gate using a gate layout of a semiconductor device. The layout includes an active region with a stepped side boundary, a plurality of gates crossing over the active region, and tabs attached to the gates on the side boundary ... | 10/07/2008 |
| 7407844 | Planar dual gate semiconductor device A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (... | 08/05/2008 |
| 7366026 | Flash memory device and method for fabricating the same, and programming and erasing method thereof A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an O... | 04/29/2008 |
| 7354832 | Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conform... | 04/08/2008 |
| 7341900 | Semiconductor device and method for manufacturing the same A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and... | 03/11/2008 |
| 7338864 | Memory device and method for fabricating the same Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a... | 03/04/2008 |
| 7323374 | Dense chevron finFET and method of manufacturing same A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single... | 01/29/2008 |
| 7314802 | Structure and method for manufacturing strained FINFET A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is ... | 01/01/2008 |
| 7309626 | Quasi self-aligned source/drain FinFET process A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present ... | 12/18/2007 |
| 7297581 | SRAM formation using shadow implantation A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant proce... | 11/20/2007 |
| 7265005 | Structure and method for dual-gate FET with SOI substrate A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins... | 09/04/2007 |
| 7256078 | High mobility plane FinFETs with equal drive strength An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. Th... | 08/14/2007 |
| 7250347 | Double-gate FETs (Field Effect Transistors) A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrod... | 07/31/2007 |
| 7244642 | Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255 | 07/17/2007 |
| 7238577 | Method of manufacturing self-aligned n and p type stripes for a superjunction device A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alt... | 07/03/2007 |
| 7233028 | Gallium nitride material devices and methods of forming the same The invention provides gallium nitride material devices, structures and methods of forming the same. The devices include a gallium nitride material formed over a substrate, such as silicon. Exemplary devices include light emitting devices (e.g., LED's, lasers), ligh... | 06/19/2007 |
| 7229867 | Process for producing a field-effect transistor and transistor thus obtained A substrate supporting a portion of a semiconductor material is used to produce a field-effect transistor. A portion of a temporary material lies between the portion of semiconductor material and the substrate. A gate is formed, which comprises an upper part in rigi... | 06/12/2007 |
| 7227183 | Polysilicon conductor width measurement for 3-dimensional FETs An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fi... | 06/05/2007 |
| 7223645 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 05/29/2007 |
| 7217623 | Fin FET and method of fabricating same A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper pa... | 05/15/2007 |
| 7208356 | Method of manufacturing multiple-gate MOS transistor having an improved channel structure Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is... | 04/24/2007 |
| 7190616 | In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical p... | 03/13/2007 |
| 7176073 | Methods of forming memory cells having diodes and electrode plates connected to source/drain regions The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body region, and further include first and second diffusion regions formed in the body region. A channel regi... | 02/13/2007 |
| 7169681 | Method of forming dual gate dielectric layer A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate... | 01/30/2007 |
| 7151018 | Method and apparatus for transistor sidewall salicidation A method for manufacturing a transistor is provided. The transistor has a substrate with an insulator on the substrate. A structure on the insulator having a structure sidewall is provided with spacers covering a portion of the structure sidewall. An exposed portion... | 12/19/2006 |
| 7151019 | Method of manufacturing a semiconductor device with different lattice properties To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second ... | 12/19/2006 |
| 7141476 | Method of forming a transistor with a bottom gate A transistor having a bottom gate formed from a layer of gate material and a channel region formed from a layer semiconductor material. In some examples, the layer of gate material is patterned separately from the layer of semiconductor material. In some examples th... | 11/28/2006 |
