Class 438/175 - Buried channel

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a Schottky gate field effect transistor
No. of patents: 42
Last issue date: 01/24/2012

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Number	Title	Issue Date
8101474	Structure and method of forming buried-channel graphene field effect device A novel buried-channel graphene device structure and method for manufacture. The new structure includes a two level channel layer comprised of a buried-channel graphene layer with an amorphous silicon top channel layer. The method for making such structure includes ...	01/24/2012
7867833	Semiconductor device utilizing a metal gate material such as tungsten and method of manufacturing the same Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the ac...	01/11/2011
7682887	Transistor having high mobility channel and methods Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a c...	03/23/2010
7544551	Technique for strain engineering in Si-based Transistors by using embedded semiconductor layers including atoms with high covalent radius By incorporating an atomic species of increased covalent radius, which may at least partially substitute germanium, a highly efficient strain mechanism may be provided, in which the risk of stress relief due to germanium conglomeration and lattice defects may be red...	06/09/2009
7342272	Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr...	03/11/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7320908	Methods of forming semiconductor devices having buried oxide patterns Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor a...	01/22/2008
7285456	Method of fabricating a fin field effect transistor having a plurality of protruding channels In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate havin...	10/23/2007
7268604	Comparator with hysteresis and method of comparing using the same A comparator includes a differential amplifier, and a hysteresis circuit. The differential amplifier amplifies a difference signal corresponding to a difference between input signals. The hysteresis circuit sets up a first transition threshold voltage and a second t...	09/11/2007
7075829	Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou...	07/11/2006
7005701	Method for fabricating a vertical NROM cell A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask ...	02/28/2006
7002187	Integrated schottky diode using buried power buss structure and method for making same An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an epitaxial layer (EPI) on the substrate region. The diode includes a ...	02/21/2006
6955969	Method of growing as a channel region to reduce source/drain junction capacitance A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a...	10/18/2005
6867078	Method for forming a microwave field effect transistor with high operating voltage A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A r...	03/15/2005
6808968	Method of manufacturing a semiconductor device It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the pres...	10/26/2004
6635518	SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created ...	10/21/2003
6620672	SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack wh...	09/16/2003
6429069	SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack wh...	08/06/2002
6376291	Process for manufacturing buried channels and cavities in semiconductor material wafers A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far...	04/23/2002
6316297	Semiconductor device and method for fabricating the same The method for fabricating a semiconductor device comprises the steps of forming on a semiconductor substrate a gate electrode, and an eave-shaped film of an inorganic material formed on the upper surface of the gate electrode and having a eave-shaped por...	11/13/2001
6258639	Sintered gate schottky barrier fet passivated by a degradation-stop layer A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a ch...	07/10/2001
6222201	Method of forming a novel self-aligned offset thin film transistor and the structure of the same The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the f...	04/24/2001
6200838	Compound semiconductor device and method of manufacturing the same In a compound semiconductor device constituting a field effect transistor having a buried p region 3, a channel region 4 is formed thin and highly doped by n-type impurity, and the buried p region 3 is formed shallowly and highly doped by p-type impurity ...	03/13/2001
6180440	Method of fabricating a recessed-gate FET without producing voids in the gate metal The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etch...	01/30/2001
6165824	Method of manufacturing a semiconductor device A crystal growth 301 is carried out by diffusing a metal element, and a nickel element is moved into regions 108 and 109 which has been doped with phosphorus. An axis coincident with the moving directions 302 and 303 of the nickel element at this time is ...	12/26/2000
6143646	Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions ...	11/07/2000
6037194	Method for making a DRAM cell with grooved transfer device A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located a...	03/14/2000
6033941	Method of forming a thin film transistor with asymmetrically arranged gate electrode and offset region A thin film transistor which includes an oxide layer containing a trench; a semiconductor layer formed on the oxide layer, including the trench; a buffer layer formed on the semiconductor layer in the trench; a gate electrode aligned on the semiconductor ...	03/07/2000
6008079	Method for forming a high density shallow trench contactless nonvolatile memory The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist...	12/28/1999
5926693	Two level transistor formation for optimum silicon utilization A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and...	07/20/1999
5894137	Semiconductor device with an active layer having a plurality of columnar crystals There is provided a technique for fabricating a thin film transistor having excellent performance. A configuration is employed in which when the thin film transistor is in an on-state, the flowing direction of the on-current coincides with the direction o...	04/13/1999
5885847	Method of fabricating a compound semiconductor device The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate. The method comprises the ...	03/23/1999
5643807	Method of manufacturing a semiconductor device comprising a buried channel field effect transistor A method of manufacturing a semiconductor device with a buried channel field effect transistor, comprising the formation of a stack of layers on a substrate with an active semiconductor layer having a non-zero aluminium (Al) content, a semiconductor cap l...	07/01/1997
5532184	Method of fabricating a semiconductor device using quantum dots or wires An undoped GaAs layer is epitaxially grown on a substrate in a crystal growth device. An undoped Alx Ga1-x As layer is then epitaxially grown to form an undoped hetero-junction structure. After this, a sample is transferred to a focu...	07/02/1996
5336626	Method of manufacturing a MESFET with an epitaxial void The present invention relates to a MESFET in which source and drain regions with inverse slopes are formed on a semi-insulating semiconductor substarate having the insulating layer by using the growth property according to the crystal direction and a chan...	08/09/1994
4837175	Making a buried channel FET with lateral growth over amorphous region A buried channel field effect transistor is provided by in situ growth of all epitaxial layers growing laterally towards each other along central amorphous semi-insulating humps (1222, 1224) and merging (1232) above the humps to epitaxially grow in single...	06/06/1989
4833095	Method for buried channel field effect transistor for microwave and millimeter frequencies utilizing ion implantation The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate i...	05/23/1989
4724220	Method for fabricating buried channel field-effect transistor for microwave and millimeter frequencies The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate i...	02/09/1988
4601096	Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate i...	07/22/1986
4503600	Process for manufacturing a buried gate field effect transistor A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal having a first impurity region as a source regi...	03/12/1985

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Class 438/175 - Buried channel