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| Number | Title | Issue Date |
| 8071434 | Method of fabricating a thin film transistor using boron-doped oxide semiconductor thin film Provided is a method of fabricating a thin film transistor including source and drain electrodes, a novel channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The method includes the steps of forming the channel layer using ... | 12/06/2011 |
| 7972915 | Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFETs A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode... | 07/05/2011 |
| 7811873 | Method for fabricating MOS-FET A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak ... | 10/12/2010 |
| 7691693 | Method for suppressing layout sensitivity of threshold voltage in a transistor array A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of intersti... | 04/06/2010 |
| 7524714 | Method for manufacturing semiconductor device Embodiments relate to a method for manufacturing a semiconductor device. According to embodiments, a gate insulating layer and a conductive layer may be formed on a semiconductor substrate. The conductive layer may be selectively etched to form a relatively thick po... | 04/28/2009 |
| 7485514 | Method for fabricating a MESFET A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel porti... | 02/03/2009 |
| 7387908 | CMOS imager with enhanced transfer of charge and low voltage operation and method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a... | 06/17/2008 |
| 7385232 | CMOS imager with enhanced transfer of charge and low voltage operation and method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a... | 06/10/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7348251 | Modulated trigger device An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizont... | 03/25/2008 |
| 7348229 | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3... | 03/25/2008 |
| 7332447 | Method of forming a contact A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and... | 02/19/2008 |
| 7323389 | Method of forming a FINFET structure A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gat... | 01/29/2008 |
| 7297580 | Methods of fabricating transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer... | 11/20/2007 |
| 7279430 | Process for fabricating a strained channel MOSFET device A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlyin... | 10/09/2007 |
| 7250313 | Method of detecting un-annealed ion implants A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is m... | 07/31/2007 |
| 7250655 | MOS transistor having a T-shaped gate electrode A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to... | 07/31/2007 |
| 7242020 | Real-time monitoring of particles in semiconductor vacuum environment An apparatus includes semiconductor processing equipment. A particle detecting integrated circuit is positioned in a vacuum environment, the particle detecting integrated circuit containing a device having a pair of conductive lines exposed to the vacuum environment... | 07/10/2007 |
| 7226824 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 06/05/2007 |
| 7226803 | Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concent... | 06/05/2007 |
| 7157299 | Nanofabrication of InAs/A1Sb heterostructures A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; w... | 01/02/2007 |
| 7135367 | Manufacturing method of semiconductor device A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is proc... | 11/14/2006 |
| 7087981 | Metal semiconductor contact, semiconductor component, integrated circuit arrangement and method The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive meta... | 08/08/2006 |
| 7078711 | Matching dose and energy of multiple ion implanters A method that is sensitive to lattice damage (also called “primary method”) is combined with an additional method that independently measures one of two parameters to which the primary method is sensitive namely dose and energy. In some embodiments, the addition... | 07/18/2006 |
| 7064388 | Semiconductor device and method for manufacturing the same An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the... | 06/20/2006 |
| 7033873 | Methods of controlling gate electrode doping, and systems for accomplishing same The present invention is generally directed to various methods of controlling gate electrode doping, and various systems for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises performing at least one process operation to form a... | 04/25/2006 |
| 7002192 | Area efficient asymmetric cellular CMOS array A cellular MOS array becomes denser by employing an asymmetric structure, in which the areas of the sources are reduced without changing the length and the width of the channel thereof, and thereby the chip size is reduced and the cost is lowered. ... | 02/21/2006 |
| 6964903 | Method of fabricating a transistor on a substrate to operate as a fully depleted structure A method provides a structure that includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The method includes forming a body region of the dual-gated M... | 11/15/2005 |
| 6956274 | TiW platinum interconnect and method of making the same A metallization stack is provided for use as a contact structure in an integrated MEMS device. The metallization stack comprises a titanium-tungsten adhesion and barrier layer formed with a platinum layer formed on top. The platinum feature is formed by sputter etch... | 10/18/2005 |
| 6956239 | Transistors having buried p-type layers beneath the source region The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer... | 10/18/2005 |
| 6926932 | Method for forming silicon oxide layer A method for forming a silicon oxide layer in the production of the polysilicon film transistor is disclosed. A plasma surface treatment is performed over a substrate after an amorphous silicon layer has been formed on the substrate by PECVD to transform a portion o... | 08/09/2005 |
| 6924180 | Method of forming a pocket implant region after formation of composite insulator spacers A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconduc... | 08/02/2005 |
| 6879006 | MOS transistor and method for fabricating the same A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer ... | 04/12/2005 |
| 6864516 | SOI MOSFET junction degradation using multiple buried amorphous layers Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator s... | 03/08/2005 |
| 6864131 | Complementary Schottky junction transistors and methods of forming the same Various methods for forming semiconductor devices are provided that include the step of implanting dopants into the devices to achieve doping concentrations that allow complementary n- and p-channel SJT behavior with devices of substantially equal gate length and ga... | 03/08/2005 |
| 6855586 | Low voltage breakdown element for ESD trigger device As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can e... | 02/15/2005 |
| 6838325 | Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second ... | 01/04/2005 |
| 6808970 | Semiconductor device having an improved strained surface layer and method of forming a strained surface layer in a semiconductor device A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xen... | 10/26/2004 |
| 6797555 | Direct implantation of fluorine into the channel region of a PMOS device Fluorine is implanted directly into the channel region of a PMOS transistor structure, thereby improving the noise and VT drift margin of device performance by introducing Si—F complexes at the substrate-gate oxide interface. ... | 09/28/2004 |
| 6793834 | Apparatus for and method of processing an object to be processed A magnetron reactive ion etching apparatus comprises: an electrode unit including electrodes facing each other through a semiconductor device; a high-frequency power source forming an electric field on the electrode unit; a dipole ring magnet; and a switching mechan... | 09/21/2004 |
