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| Number | Title | Issue Date |
| 7972914 | Semiconductor device with FinFET and method of fabricating the same A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of ... | 07/05/2011 |
| 7763504 | Method for manufacturing silicon carbide semiconductor device A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion;... | 07/27/2010 |
| 7432134 | Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme... | 10/07/2008 |
| 7413958 | GaN-based permeable base transistor and method of fabrication An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. ... | 08/19/2008 |
| 7387937 | Thermal dissipation structures for FinFETs A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer include... | 06/17/2008 |
| 7382024 | Low threshold voltage PMOS apparatus and method of fabricating the same A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter... | 06/03/2008 |
| 7371697 | Ion-assisted oxidation methods and the resulting structures Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over d... | 05/13/2008 |
| 7352036 | Semiconductor power device having a top-side drain using a sinker trench A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extend... | 04/01/2008 |
| 7323389 | Method of forming a FINFET structure A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gat... | 01/29/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7304361 | Inexpensive organic solar cell and method of producing same The present invention proposes an organic photovoltaic component, particularly an organic solar cell, whose electrode is implemented as unstructured and is provided with a passivation layer, so that the passivated electrode layer acts functionally as a structured el... | 12/04/2007 |
| 7273771 | Common MOSFET process for plural devices A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusio... | 09/25/2007 |
| 7259048 | Vertical replacement-gate silicon-on-insulator transistor An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin s... | 08/21/2007 |
| 7238976 | Schottky barrier rectifier and method of manufacturing the same A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second do... | 07/03/2007 |
| 7192872 | Method of manufacturing semiconductor device having composite buffer layer The present invention relates to a method of manufacturing semiconductor device with composite buffer layers. The method includes etching grooves in n type and p type semiconductor wafers respectively. The areas of grooves in n type wafer just correspond to the area... | 03/20/2007 |
| 7176089 | Vertical dual gate field effect transistor A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The ... | 02/13/2007 |
| 7161213 | Low threshold voltage PMOS apparatus and method of fabricating the same A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter... | 01/09/2007 |
| 7151016 | Method of manufacturing a semiconductor device that includes a hydrogen concentration depth profile A method for manufacturing a semiconductor device having a circuit made up by a TFT (Thin Film Transistor) having GOLD (Gate-Drain Overlapped LDD) structure, which an LDD region overlaps which a portion of a gate electrode, wherein the formation of a concentration d... | 12/19/2006 |
| 7138682 | Organic thin-film transistor and method of manufacturing the same A thin-film transistor includes a substrate (10), a gate electrode (20) provided on a portion of the substrate, an insulation layer (30) arranged to cover the gate electrode and the substrate, a source or drain (40) provided on the insula... | 11/21/2006 |
| 7109516 | Strained-semiconductor-on-insulator finFET device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... | 09/19/2006 |
| 7105895 | Epitaxial SiObarrier/insulation layer A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects... | 09/12/2006 |
| 7098093 | HEMT device and method of making A HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN havi... | 08/29/2006 |
| 7084455 | Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, a... | 08/01/2006 |
| 7084475 | Lateral conduction Schottky diode with plural mesas A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the ... | 08/01/2006 |
| 7078280 | Vertical replacement-gate silicon-on-insulator transistor An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin s... | 07/18/2006 |
| 7060539 | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby An FET device with a source island and a drain island is formed on a horizontal surface of a substrate comprising an insulating material. A channel structure formed over the horizontal surface of the substrate, which connects between the drain and the source, compri... | 06/13/2006 |
| 7033876 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 04/25/2006 |
| 7029956 | Memory system capable of operating at high temperatures and method for fabricating the same A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each... | 04/18/2006 |
| 6974733 | Double-gate transistor with enhanced carrier mobility There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel. ... | 12/13/2005 |
| 6955969 | Method of growing as a channel region to reduce source/drain junction capacitance A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a... | 10/18/2005 |
| 6929983 | Method of forming a current controlling device A current-controlling device comprising a first conductor, a second conductor, and a tunneling barrier comprising a first insulating layer between the first conductor and the second conductor. The tunneling barrier electrically isolates the first conductor from the ... | 08/16/2005 |
| 6908828 | Support-integrated donor wafers for repeated thin donor layer separation Processes that may be used in producing electronic, optoelectronic, or optical components may be provided. The processes may involve preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of a semiconductor m... | 06/21/2005 |
| 6855604 | Method for fabricating metal-oxide semiconductor transistor The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a... | 02/15/2005 |
| 6855603 | Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon n... | 02/15/2005 |
| 6815294 | Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon n... | 11/09/2004 |
| 6777295 | Method of fabricating trench power MOSFET A method of fabricating trench power MOSFET is described. A first etching step is performed on a substrate to form a plurality of trenches and the substrate has a first doped region and a second doped region and serves as a drain region. A gate oxide layer and a pol... | 08/17/2004 |
| 6770534 | Ultra small size vertical MOSFET device and method for the manufacture thereof The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive lay... | 08/03/2004 |
| 6750095 | Integrated circuit with vertical transistors A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is... | 06/15/2004 |
| 6740910 | Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that ... | 05/25/2004 |
| 6693005 | Trench capacitor with expanded area and method of making the same A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar... | 02/17/2004 |
