Class 438/172 - Having heterojunction (e.g., HEMT, MODFET, etc.)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a Schottky gate field effect transistor
No. of patents: 383
Last issue date: 12/13/2011

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Number	Title	Issue Date
8076188	Method of manufacturing a semiconductor device A manufacturing method of a semiconductor device including a protecting element with a p-n junction which can be formed in the same process as that of a p-channel junction FET while the junction FET is formed in simple manufacturing process is provided. In the metho...	12/13/2011
8043906	Method of forming a III-nitride selective current carrying device including a contact in a recess A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is i...	10/25/2011
8039329	Field effect transistor having reduced contact resistance and method for fabricating the same A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1−yN (wherein 0	10/18/2011
8034675	Semiconductor buffer architecture for III-V devices on silicon substrates A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 t...	10/11/2011
8026132	Leakage barrier for GaN based HEMT active device An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities for...	09/27/2011
8012816	Double pass formation of a deep quantum well in enhancement mode III-V devices A quantum well is formed for a deep well III-V semiconductor device using double pass patterning. In one example, the well is formed by forming a first photolithography pattern over terminals on a material stack, etching a well between the terminals using the first ...	09/06/2011
8003452	Compound semiconductor device and manufacturing method thereof A compound semiconductor device includes a carrier transit layer formed over a substrate; a carrier supply layer formed over the carrier transit layer; a first metal film and a second metal film formed over the carrier supply layer; a first Al comprising film formed...	08/23/2011
7989278	Compound semiconductor device and method for fabricating the same The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron su...	08/02/2011
7968391	High voltage GaN-based transistor structure A high voltage and high power gallium nitride (GaN) transistor structure is disclosed. A plurality of structural epitaxial layers including a GaN buffer layer is deposited on a substrate. A GaN termination layer is deposited on the plurality of structural epitaxial ...	06/28/2011
7939391	III-Nitride devices with recessed gates III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adja...	05/10/2011
7915104	Methods and compositions for preparing tensile strained Ge on GeSnbuffered semiconductor substrates The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge1-ySny buffer layer on a semiconductor substrate and forming a tensile strained Ge layer on the Ge1-ySny buffer layer ...	03/29/2011
7902012	High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-ju...	03/08/2011
7892902	Group III-V devices with multiple spacer layers A group III-V material device has multiple spacer regions above a quantum well channel region. A high-k value gate dielectric is formed on an InGaAs spacer above the quantum well channel region while there are InAlAs spacer regions under contact regions. ...	02/22/2011
7871874	Transistor of semiconductor device and method of fabricating the same Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a secon...	01/18/2011
7855108	Semiconductor heterojunction devices based on SiC A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC...	12/21/2010
7851284	Method for making GaN-based high electron mobility transistor A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through t...	12/14/2010
7811872	Method for manufacturing a field effect transistor having a field plate An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose th...	10/12/2010
7807521	Nitride semiconductor light emitting device and method of manufacturing the same A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer formed on a substrate, an active layer formed on the n-type nitride se...	10/05/2010
7772055	AlGaN/GaN high electron mobility transistor devices The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin...	08/10/2010
7749828	Method of manufacturing group III Nitride Transistor Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 co...	07/06/2010
7713803	Mechanism for forming a remote delta doping layer of a quantum well structure A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well. ...	05/11/2010
7713802	Method of sulfuration treatment for a strained InAlAs/InGaAs metamorphic high electron mobility transistor This invention relates to a method of sulfuration treatment for InAlAs/InGaAs metamorphic high electron mobility transistor (MHEMT), and the sulfuration treatment is applied to the InAlAs/InGaAs MHEMT for a passivation treatment for Gate, in order to increase initia...	05/11/2010
7678629	Method for fabricating a recessed ohmic contact for a PHEMT structure According to an exemplary embodiment, a PHEMT (pseudomorphic high electron mobility transistor) structure includes a conductive channel layer. The PHEMT structure further includes at least one doped layer situated over the conductive channel layer. The at least one ...	03/16/2010
7678628	Methods of fabricating nitride-based transistors with a cap layer and a recessed gate An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may f...	03/16/2010
7674666	Fabrication of semiconductor device having composite contact A method of fabricating a semiconductor device with a composite contact is provided. The fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure. The composite contact is formed by forming a DC conducting electrode at...	03/09/2010
7662682	Highly uniform group III nitride epitaxial layers on 100 millimeter diameter silicon carbide substrates A method for epitaxial growth of Group III nitrides on a substrate using source gases consistent with metal organic chemical vapor deposition is provided. A heterostructure formed from two Group III nitride epitaxial layers is grown on a substrate in an atmosphere c...	02/16/2010
7608496	High speed GE channel heterostructures for field effect devices A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer h...	10/27/2009
7601573	Method for producing nitride semiconductor device A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen...	10/13/2009
7598131	High power-low noise microwave GaN heterojunction field effect transistor A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. ...	10/06/2009
7592211	Methods of fabricating transistors including supported gate electrodes Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside...	09/22/2009
7569442	High speed lateral heterojunction MISFETS realized by 2-dimensional bandgap engineering and methods thereof A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-ju...	08/04/2009
7560323	Compound semiconductor device and method of fabricating the same In formation-by-growth of an AlGaN layer 3 as having a double-layered structure, a non-doped AlGaN layer (i-AlGaN layer) having an Al compositional ratio of approximately 15% is formed to a thickness of approximately 3 nm on an i-GaN layer, and further thereo...	07/14/2009
7541232	Method for fabrication of devices in a multi-layer structure A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate reces...	06/02/2009
7531397	Method for manufacturing a semiconductor device on GAN substrate having surface bidirectionally inclined toward <1-100> and <11-20> directions relative to {0001} crystal planes A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the su...	05/12/2009
7531396	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different f...	05/12/2009
7498213	Methods of fabricating a semiconductor substrate for reducing wafer warpage Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of th...	03/03/2009
7494855	Compound semiconductor device and method for fabricating the same The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron su...	02/24/2009
7459356	High voltage GaN-based transistor structure The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operati...	12/02/2008
7432142	Methods of fabricating nitride-based transistors having regrown ohmic contact regions Transistor fabrication includes forming a nitride-based channel layer on a substrate, forming a barrier layer on the nitride-based channel layer, forming a contact recess in the barrier layer to expose a contact region of the nitride-based channel layer, forming a c...	10/07/2008
7425488	Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask struct...	09/16/2008

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Class 438/172 - Having heterojunction (e.g., HEMT, MODFET, etc.)