Celebrity Inventors
Actress Jamie Lee Curtis is a patented inventor - she created a diaper equipped with a premoistened baby wipe. And that's no act!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8187928 | Methods of forming integrated circuits A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in... | 05/29/2012 |
| 8178399 | Production method for semiconductor device An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate elect... | 05/15/2012 |
| 8163605 | Production method for semiconductor device It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be ob... | 04/24/2012 |
| 8153483 | Semiconductor device having a vertical transistor and method for manufacturing the same A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to cont... | 04/10/2012 |
| 8043903 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding port... | 10/25/2011 |
| 7943444 | Vertical floating body cell of a semiconductor device and method for fabricating the same A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconduc... | 05/17/2011 |
| 7923313 | Method of making transistor including reentrant profile A method of manufacturing a transistor includes providing a substrate including in order an electrically conductive material layer and an electrically insulating material layer; depositing a resist material layer over the electrically insulating material layer; patt... | 04/12/2011 |
| 7902005 | Method for fabricating a fin-shaped semiconductor structure and a fin-shaped semiconductor structure A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin. ... | 03/08/2011 |
| 7879659 | Methods of fabricating semiconductor devices including dual fin structures Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed... | 02/01/2011 |
| 7799623 | Method for manufacturing semiconductor device having LDMOS transistor A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a ... | 09/21/2010 |
| 7785943 | Method for forming a multi-gate device with high k dielectric for channel top surface Method for providing a transistor that includes the steps of providing a silicon on insulator layer, providing a silicon oxide insulation layer, providing a dielectric layer, removing at least a portion of the silicon oxide insulation layer and the dielectric layer ... | 08/31/2010 |
| 7682885 | Method for fabricating vertical channel transistor in a semiconductor device A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer a... | 03/23/2010 |
| 7674661 | Memory device and method of manufacturing the same In a memory device and a method of manufacturing the memory device, a pair of channel layers included in the memory device may be formed on a sidewall of the sacrificial single crystalline layer pattern located on a protrusion of a semiconductor substrate. According... | 03/09/2010 |
| 7592210 | Semiconductor device with increased channel area and decreased leakage current The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The rec... | 09/22/2009 |
| 7531395 | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an opening into a silicate glass-comprising material received over a mono... | 05/12/2009 |
| 7528022 | Method of forming fin field effect transistor using damascene process A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a pa... | 05/05/2009 |
| 7485509 | Semiconductor device provided by silicon carbide substrate and method for manufacturing the same A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field ... | 02/03/2009 |
| 7439135 | Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and exten... | 10/21/2008 |
| 7435637 | Quantum wire gate device and method of making same The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The m... | 10/14/2008 |
| 7436019 | Non-volatile memory cells shaped to increase coupling to word lines A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also... | 10/14/2008 |
| 7435982 | Laser-driven light source An apparatus for producing light includes a chamber and an ignition source that ionizes a gas within the chamber. The apparatus also includes at least one laser that provides energy to the ionized gas within the chamber to produce a high brightness light. The laser ... | 10/14/2008 |
| 7432134 | Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme... | 10/07/2008 |
| 7427547 | Three-dimensional high voltage transistor and method for manufacturing the same A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from ea... | 09/23/2008 |
| 7410844 | Device fabrication by anisotropic wet etch A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substan... | 08/12/2008 |
| 7388245 | Semiconductor device, method for manufacturing the semiconductor device and portable electronic device provided with the semiconductor device A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in it... | 06/17/2008 |
| 7381595 | High-density plasma oxidation for enhanced gate oxide performance A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depo... | 06/03/2008 |
| 7382024 | Low threshold voltage PMOS apparatus and method of fabricating the same A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter... | 06/03/2008 |
| 7364971 | Method for manufacturing semiconductor device having super junction construction A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is ... | 04/29/2008 |
| 7352034 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be inte... | 04/01/2008 |
| 7351620 | Methods of forming semiconductor constructions The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/01/2008 |
| 7341896 | Method of manufacturing a vertical MOS transistor In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. A first insulating film is deposited over the main ... | 03/11/2008 |
| 7335598 | Chemical-mechanical polishing method A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a ch... | 02/26/2008 |
| 7335943 | Ultrascalable vertical MOS transistor with planar contacts A doped silicon block or island, formed above a drain electrode in substrate of a die or chip, has a height corresponding to the desired length of a channel. A source electrode is formed above the silicon island and allows for contact from above. Contact from above ... | 02/26/2008 |
| 7332385 | Method of manufacturing a semiconductor device that includes gettering regions A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline ... | 02/19/2008 |
| 7329567 | Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemic... | 02/12/2008 |
| 7326617 | Method of fabricating a three-dimensional multi-gate device A method for fabricating a three-dimensional multi-gate device includes steps of providing a semiconductor substrate and forming a silicon fin on the semiconductor substrate, the silicon fin having a top surface and two side surfaces; forming a gate structure on the... | 02/05/2008 |
| 7323373 | Method of forming a semiconductor device with decreased undercutting of semiconductor material A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer.... | 01/29/2008 |
| 7321166 | Wiring board having connecting wiring between electrode plane and connecting pad It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board f... | 01/22/2008 |
| 7314783 | Method of fabricating contact line of liquid crystal display device A contact line structure for a liquid crystal display device includes a metal line on an array substrate, a silicide layer on the metal line, an insulating layer having a contact hole exposing a first portion of the silicide layer, and a transparent conducting termi... | 01/01/2008 |
| 7301168 | Organic light emitting diode display and manufacturing method with partition and emission regions to improve emission characteristics An organic light emitting display according to an embodiment of the invention includes: a substrate; a first electrode disposed on the substrate; a first partition disposed on the first electrode and having an opening exposing the first electrode; a second partition... | 11/27/2007 |
