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| Number | Title | Issue Date |
| 8183100 | Transistor with embedded SI/GE material having enhanced across-substrate uniformity In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystal... | 05/22/2012 |
| 8173497 | Semiconductor device preventing floating body effect in a peripheral region thereof and method for manufacturing the same A semiconductor device having a cell region and a peripheral region includes an silicon on insulator (SOI) substrate having a stack structure of a silicon substrate, a buried insulation layer, and a silicon layer. An epi-silicon layer is formed in the buried insulat... | 05/08/2012 |
| 8105887 | Inducing stress in CMOS device A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field... | 01/31/2012 |
| 8053292 | Semiconductor device and method of manufacturing semiconductor device The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate elect... | 11/08/2011 |
| 8030143 | Method of forming a display device by using separate masks in forming source and drain regions of MOS transistors A method of forming a display device is provided. The method includes the following steps: providing a substrate which includes a driving circuit region and a pixel region; forming a first island and a second island in the driving circuit region on the substrate wit... | 10/04/2011 |
| 7968385 | Thin film transistor panel and fabricating method thereof A thin film transistor panel includes; an insulating substrate, a gate line including a gate electrode disposed on the insulating substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, the semi... | 06/28/2011 |
| 7892900 | Integrated circuit system employing sacrificial spacers An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made f... | 02/22/2011 |
| 7838349 | Semiconductor device and method of manufacturing the same A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which sup... | 11/23/2010 |
| 7833848 | Method for removing hard masks on gates in semiconductor manufacturing process A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. T... | 11/16/2010 |
| 7816191 | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the ... | 10/19/2010 |
| 7795082 | Method of fabricating thin film transistor A method of fabricating a CMOS thin film transistor includes: providing a substrate; forming an amorphous silicon layer on the substrate; performing a first annealing process on the substrate and crystallizing the amorphous silicon layer into a polysilicon layer; pa... | 09/14/2010 |
| 7790527 | High-voltage silicon-on-insulator transistors and methods of manufacturing the same In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) laye... | 09/07/2010 |
| 7790528 | Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried o... | 09/07/2010 |
| 7759179 | Multi-gated, high-mobility, density improved devices Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the cen... | 07/20/2010 |
| 7713801 | Method of making a semiconductor structure utilizing spacer removal and semiconductor structure A method for making a semiconductor structure (10) includes providing a wafer with a structure (16) having a sidewall, forming a sidewall spacer (22) adjacent to the sidewall, and forming a layer of material (28) over the wafer including ... | 05/11/2010 |
| 7700420 | Integrated circuit with different channel materials for P and N channel transistors and method therefor A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a s... | 04/20/2010 |
| 7642141 | Manufacturing method for display device A manufacturing method for a display device having a first conductive type thin film transistor and a second conductive type thin film transistor, comprising the steps of: in formation regions for a first conductive type thin film transistor and a second conductive ... | 01/05/2010 |
| 7625786 | Semiconductor device and method of manufacturing the same Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impu... | 12/01/2009 |
| 7605027 | Method of fabricating a bipolar transistor A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned i... | 10/20/2009 |
| 7588973 | Semiconductor device and method of manufacturing the same In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions ... | 09/15/2009 |
| 7585711 | Semiconductor-on-insulator (SOI) strained active area transistor A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insul... | 09/08/2009 |
| 7582516 | CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region co... | 09/01/2009 |
| 7566600 | SOI device with reduced drain induced barrier lowering A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and ... | 07/28/2009 |
| 7560319 | Method for fabricating a semiconductor device A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer struct... | 07/14/2009 |
| 7544548 | Trench liner for DSO integration A semiconductor process and apparatus provide a shallow trench isolation region (96) with a trench liner (95, 104) for use in a hybrid substrate device (21) by lining a first trench with a first trench liner (95), and then lining a second... | 06/09/2009 |
| 7537982 | Method and structure for isolating substrate noise An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit regi... | 05/26/2009 |
| 7524710 | Radiation-hardened silicon-on-insulator CMOS device, and method of making the same A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire... | 04/28/2009 |
| 7510917 | Active matrix display device and method of manufacturing the same In an active matrix display device integrated with peripheral drive circuits, an image sensor is provided on the same substrate as a pixel matrix and peripheral drive circuits. The image sensor is formed on the substrate having pixel electrodes, pixel TFTs connected... | 03/31/2009 |
| 7504289 | Process for forming an electronic device including transistor structures with sidewall spacers An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having... | 03/17/2009 |
| 7485508 | Two-sided semiconductor-on-insulator structures and methods of manufacturing the same Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier... | 02/03/2009 |
| 7479418 | Methods of applying substrate bias to SOI CMOS circuits The present invention relates to methods for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-... | 01/20/2009 |
| 7476578 | Process for finFET spacer formation A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about t... | 01/13/2009 |
| 7470573 | Method of making CMOS devices on strained silicon on glass A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer ... | 12/30/2008 |
| 7439088 | Liquid crystal display device and fabricating method thereof An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line crossing each other to define a pixel region, a thin film transistor at a crossing of the gate and data lines, a metal pattern over the gate line, a passivation ... | 10/21/2008 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7432149 | CMOS on SOI substrates with hybrid crystal orientations Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming ... | 10/07/2008 |
| 7425477 | Manufacturing method of thin film transistor including implanting ions through polysilicon island and into underlying buffer layer A manufacturing method of a thin film transistor is provided. A buffer layer is formed on a substrate, and then a first and a second poly-silicon island are formed thereon. A gate-insulating layer is formed on the substrate, and a first and a second gate are formed ... | 09/16/2008 |
| 7422971 | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of formin... | 09/09/2008 |
| 7422935 | Method for manufacturing semiconductor device, and semiconductor device and electronic device It is an object of the present invention to manufacture a semiconductor device easily and to provide a semiconductor device whose cost is reduced. According to the present invention, a thin film integrated circuit provided over a base insulating layer can be prevent... | 09/09/2008 |
| 7419859 | Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistan... | 09/02/2008 |
