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| Number | Title | Issue Date |
| 8158468 | Production method for surrounding gate transistor semiconductor device Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar se... | 04/17/2012 |
| 8148216 | Nonvolatile semiconductor memory and process of producing the same A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory ce... | 04/03/2012 |
| 8133771 | Display device and manufacturing method of the same A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film ... | 03/13/2012 |
| 8093111 | Semiconductor device including partial silicon on insulator fin structure and method for fabricating the same A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and formi... | 01/10/2012 |
| 8058114 | Method of manufacturing the array substrate capable of decreasing a line resistance A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is for... | 11/15/2011 |
| 8030142 | Semiconductor device and method of designing the semiconductor device A semiconductor device according to an embodiment of the present invention includes: a first region having patterns formed based on grid points as intersections of grid lines; and a second region including a plurality of layout cells an outer edge of which is define... | 10/04/2011 |
| 8012814 | Method of forming a high performance fet and a high voltage fet on a SOI substrate A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectri... | 09/06/2011 |
| 8008137 | Method for fabricating 1T-DRAM on bulk silicon An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRA... | 08/30/2011 |
| 7968384 | Stacked transistors and process A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsul... | 06/28/2011 |
| 7943442 | SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective... | 05/17/2011 |
| 7939387 | Patterned thin SOI A process for treating a structure to prepare it for electronics or optoelectronics applications. The structure includes a bulk substrate, an oxide layer, and a semiconductor layer, and the process includes providing a masking to define on the semiconductor layer a ... | 05/10/2011 |
| 7883945 | Array substrate and method of manufacturing the same A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A ... | 02/08/2011 |
| 7858455 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-s... | 12/28/2010 |
| 7855107 | Semiconductor device, electro-optical device, and method for manufacturing semiconductor device A method for manufacturing a semiconductor apparatus, the method including: aligning, on a temporal substrate, the plurality of device chips approximately in an L-shape, a plurality of groups of device chips, each group of device chips including a plurality of devic... | 12/21/2010 |
| 7824971 | Semiconductor device and method for manufacturing the same A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. Th... | 11/02/2010 |
| 7755888 | Mounting apparatus for electronic device An exemplary mounting apparatus for an electronic device includes a base, a cover covering the base, and an ejection mechanism. The base includes a first receptacle portion for receiving the electronic device, and a second receptacle portion for receiving the ejecti... | 07/13/2010 |
| 7674660 | Multilevel semiconductor device and method of manufacturing the same A method of fabricating a multilevel semiconductor integrated circuit is provided, comprising: forming on a first active semiconductor structure a first plurality of transistors with respective gate structures disposed on a first substrate and source or drain region... | 03/09/2010 |
| 7666720 | Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations A method of forming a current mirror device for an integrated circuit includes configuring a reference current source; forming a first field effect transistor (FET) in series with the reference current source, the first FET of a first conductivity type formed on a f... | 02/23/2010 |
| 7611931 | Semiconductor structures with body contacts and fabrication methods thereof A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor subs... | 11/03/2009 |
| 7572687 | Semiconductor device and manufacturing method of the same Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide lay... | 08/11/2009 |
| 7550332 | Non-planar transistor having germanium channel region and method of manufacturing the same Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body.... | 06/23/2009 |
| 7521300 | Semiconductor device substrate including a single-crystalline layer and method of manufacturing semiconductor device substrate A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the patt... | 04/21/2009 |
| 7439108 | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region ... | 10/21/2008 |
| 7439135 | Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and exten... | 10/21/2008 |
| 7439112 | Semiconductor device using partial SOI substrate and manufacturing method thereof A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer dispo... | 10/21/2008 |
| 7435633 | Electroluminescence device, manufacturing method thereof, and electronic apparatus An organic electroluminescence device including: a substrate having conductivity on at least one side; a first insulation film, formed on one side of the substrate, while having an aperture which partially exposes the same side of the substrate; a semiconductor film... | 10/14/2008 |
| 7402466 | Strained silicon CMOS on hybrid crystal orientations Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material,... | 07/22/2008 |
| 7396710 | Fin-type semiconductor device with low contact resistance and its manufacture method A semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, having a pair of generally vertical side walls and an upper surface coupling the side walls; an insulated gate electrode structure traversing an intermediate portion of th... | 07/08/2008 |
| 7393730 | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region ... | 07/01/2008 |
| 7384829 | Patterned strained semiconductor substrate and device A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is... | 06/10/2008 |
| 7382029 | Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of th... | 06/03/2008 |
| 7372101 | Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the t... | 05/13/2008 |
| 7372720 | Methods and apparatus for decreasing soft errors and cell leakage in integrated circuit structures Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably include memory cells that utilize thin-film transistors (“TFTs”) for the pull-up and pull-down transistors... | 05/13/2008 |
| 7368334 | Silicon-on-insulator chip with multiple crystal orientations A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation a... | 05/06/2008 |
| 7368337 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconduc... | 05/06/2008 |
| 7361534 | Method for fabricating SOI device A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectr... | 04/22/2008 |
| 7351620 | Methods of forming semiconductor constructions The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/01/2008 |
| 7351993 | Rare earth-oxides, rare earth-nitrides, rare earth-phosphides and ternary alloys with silicon Atomic layer epitaxy (ALE) is applied to the fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with sil... | 04/01/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7326603 | Semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device A semiconductor device includes a semiconductor substrate that has an oxide film selectively formed on a part thereof; a semiconductor layer that is formed on the oxide film by epitaxial growth; a first gate electrode that is formed on the semiconductor layer; first... | 02/05/2008 |
