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| Number | Title | Issue Date |
| 8168480 | Fabricating method for forming integrated structure of IGBT and diode An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared wi... | 05/01/2012 |
| 8153481 | Semiconductor power device with passivation layers A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N− type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (P... | 04/10/2012 |
| 8119460 | Semiconductor device and method of forming the same A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed ... | 02/21/2012 |
| 8110449 | Semiconductor device and method of manufacturing the same The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide fi... | 02/07/2012 |
| 8110448 | Two terminal multi-channel ESD device and method therefor In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. ... | 02/07/2012 |
| 8039323 | Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor layer with an impurity of a first conductivity type diffused therein, and a local insulating layer, source layer, and a drain layer formed therein. The drain layer has an impurity of a second conductivity type opposite... | 10/18/2011 |
| 7972909 | Guard ring extension to prevent reliability failures An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping la... | 07/05/2011 |
| 7932133 | Circuit protection method using diode with improved energy impulse rating A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a sub... | 04/26/2011 |
| 7910411 | Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction st... | 03/22/2011 |
| 7871867 | Semiconductor device and method of manufacturing the same A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conducti... | 01/18/2011 |
| 7863110 | Semiconductor device and method for fabricating the same A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impuri... | 01/04/2011 |
| 7838343 | Semiconductor structure and fabrication method thereof A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defi... | 11/23/2010 |
| 7790520 | Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top... | 09/07/2010 |
| 7776660 | Manufacturing method of a semiconductor device Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collec... | 08/17/2010 |
| 7759173 | Methods for charge dissipation in integrated circuits Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation ... | 07/20/2010 |
| 7713794 | Manufacturing method of a semiconductor device A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor subs... | 05/11/2010 |
| 7642139 | Semiconductor device production method and semiconductor device A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to rea... | 01/05/2010 |
| 7611927 | Method of minimizing kerf width on a semiconductor substrate panel A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining p... | 11/03/2009 |
| 7598128 | Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si t... | 10/06/2009 |
| 7572683 | Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the ... | 08/11/2009 |
| 7547586 | Method of making a self aligned ion implanted gate and guard ring structure for use in a sit A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protec... | 06/16/2009 |
| 7432135 | Semiconductor device and method of manufacturing the same A semiconductor device, including: a semiconductor substrate of a first conductivity type having a first and second major surfaces; a first conductivity type semiconductor layer formed on the first major surface of the semiconductor substrate; a base layer of a seco... | 10/07/2008 |
| 7427800 | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 09/23/2008 |
| 7419877 | Methods of fabricating silicon carbide devices including multiple floating guard ring edge termination Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on t... | 09/02/2008 |
| 7411257 | Semiconductor device having guard ring and manufacturing method thereof An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact com... | 08/12/2008 |
| 7384826 | Method of forming ohmic contact to a semiconductor body A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance... | 06/10/2008 |
| 7368792 | MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo... | 05/06/2008 |
| 7364971 | Method for manufacturing semiconductor device having super junction construction A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is ... | 04/29/2008 |
| 7355260 | Schottky device and method of forming A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the fi... | 04/08/2008 |
| 7355226 | Power semiconductor and method of fabrication This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a po... | 04/08/2008 |
| 7339249 | Semiconductor device An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p typ... | 03/04/2008 |
| 7335565 | Metal-oxide-semiconductor device having improved performance and reliability A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and... | 02/26/2008 |
| 7332380 | Pattern design method and program of a semiconductor device including dummy patterns According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy ... | 02/19/2008 |
| 7326596 | High voltage power device with low diffusion pipe resistance A method for forming a high voltage semiconductor power device comprises providing a first dopant source of first conductivity on an upper surface of a substrate of second conductivity. A second dopant source of first conductivity is provided on a lower surface of t... | 02/05/2008 |
| 7311385 | Micro-fluid ejecting device having embedded memory device A semiconductor substrate for a micro-fluid ejecting device. The semiconductor substrate includes a plurality of fluid ejection devices disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejec... | 12/25/2007 |
| 7301201 | High voltage device having polysilicon region in trench and fabricating method thereof A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon... | 11/27/2007 |
| 7282386 | Schottky device and method of forming A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias... | 10/16/2007 |
| 7282750 | Semiconductor component comprising areas with a high platinum concentration A structure formed in a semiconductor substrate having at least one area having a high concentration of atoms of a metal such as platinum or gold, in which the area is surrounded with at least one first trench penetrating into the substrate. ... | 10/16/2007 |
| 7265438 | RF seal ring structure Described is a method where a seal ring is formed by stacking interconnected conductive layers along the perimeter of an integrated circuit (IC). The seal ring is formed continuously around the IC perimeter using a conductive chain with two distinct widths. Each sec... | 09/04/2007 |
| 7253486 | Field plate transistor with reduced field plate resistance In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The f... | 08/07/2007 |
