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| Number | Title | Issue Date |
| 7332448 | Manufacturing method of semiconductor device and semiconductor manufacturing device A manufacturing method of a semiconductor device, comprises; a process of heat-treating a semiconductor substrate under the ordinary pressure and in an oxidizing atmosphere; and a process of heat-treating the semiconductor substrate under the ordinary pressure and i... | 02/19/2008 |
| 7332361 | Xerographic micro-assembler Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a so... | 02/19/2008 |
| 7329551 | Manufacturing and testing of electrostatic discharge protection circuits A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding... | 02/12/2008 |
| 7330037 | Electrical characteristic measuring probe and method of manufacturing the same In an electrical characteristic measuring probe of the present invention constructed by assembling a plurality of probe parts, each comprising a base portion, a plurality of terminal portions extended outward from one end of the base portion, wiring patterns extende... | 02/12/2008 |
| 7330042 | Substrate inspection system, substrate inspection method, and substrate inspection apparatus It is an object of the present invention to provide a substrate inspection system, a substrate inspection method, and a substrate inspection apparatus for realizing efficient operation of inspecting both a large region and a small region of a substrate. The present ... | 02/12/2008 |
| 7328830 | Structure and method for bonding to copper interconnect structures An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attachin... | 02/12/2008 |
| 7329550 | Method for analyzing the structure of deep trench capacitors and a preparation method thereof A method for analyzing the structure of deep trench capacitors and a preparation method thereof are described. A protective layer is formed on a selected inspection area. Overlying circuit layers and an upper portion of a substrate, surrounding the selected inspecti... | 02/12/2008 |
| 7330260 | Method for measuring ion-implanted semiconductors with improved repeatability The repeatability of wafer uniformity measurements can be increased by taking spatially averaged measurements of wafer response. By increasing the time over which measurements are obtained, the amount of noise can be significantly reduced, thereby improving the repe... | 02/12/2008 |
| 7329549 | Monitoring method of processing state and processing unit The present invention is a monitoring method of monitoring a change of a processing state of an object to be processed when a predetermined process is conducted to the object to be processed by using a processing unit. The method includes: a step of respectively set... | 02/12/2008 |
| 7330025 | Touchdown counter for integrated circuit testers A touch-down counter is provided that maintains a count of how many times integrated circuits are placed into contact with a contactor in a test handler. The test handler has a work press that places integrated circuits into contact with pogo pins in the contactor. ... | 02/12/2008 |
| 7327598 | High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical g... | 02/05/2008 |
| 7327150 | Integrated circuit package resistance measurement For one embodiment, an integrated circuit includes a node to couple one or more components to the integrated circuit to carry current through a package for the integrated circuit. The integrated circuit also includes a monitor to measure a resistance of the package ... | 02/05/2008 |
| 7327475 | Measuring a process parameter of a semiconductor fabrication process using optical metrology To measure a process parameter of a semiconductor fabrication process, the fabrication process is performed on a first area using a first value of the process parameter. The fabrication process is performed on a second area using a second value of the process parame... | 02/05/2008 |
| 7327041 | Semiconductor package and a method for producing the same A semiconductor package includes: a semiconductor chip having circuits formed on a surface, and having a thickness of 0.5 μm or more and 100 μm or less; and an adhesive resin layer provided so as to cover the surface of the semiconductor chip on which the circuits... | 02/05/2008 |
| 7326066 | Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same An adapter and method for aligning and connecting the external leads of at least one integrated circuit device to conductors on a substrate of a multi-chip module. The adapter includes a component frame configured to receive the integrated circuit device. The compon... | 02/05/2008 |
| 7326581 | System, method and apparatus for automatic control of an RF generator for maximum efficiency A method of dynamically adjusting a RF generator to an instantaneous resonant frequency of a transducer includes providing an RF input signal from an oscillator to the RF generator and measuring a supply voltage applied to the RF generator. A peak voltage in the RF ... | 02/05/2008 |
| 7328381 | Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memo... | 02/05/2008 |
| 7323899 | System and method for resumed probing of a wafer According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set identifies at least one unprobed die supported on the surface of the wafer. The method also includes dete... | 01/29/2008 |
| 7325206 | Electronic design for integrated circuits based process related variations An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjust... | 01/29/2008 |
| 7324917 | Method, system, and software for evaluating characteristics of a surface with reference to its edge A method and software is disclosed for evaluating characteristics, such as flatness, of a surface of a sample having an edge, comprising selecting an evaluation area having an area surface and a boundary, at least one portion of which is definable with reference to ... | 01/29/2008 |
| 7324866 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided in which it is possible to perform process control taking account of wafer information and to deal with the process control in which a recipe is change from one wafer to another. The method comprises step... | 01/29/2008 |
| 7323116 | Methods and apparatus for monitoring a process in a plasma processing system by measuring self-bias voltage A method for in-situ monitoring a process in a plasma processing system having a plasma processing chamber is disclosed. The method includes positioning a substrate in the plasma processing chamber. The method also includes striking a plasma within the plasma proces... | 01/29/2008 |
| 7323359 | Mounting method for a semiconductor component A mounting method for a semiconductor component. The method includes application of solder material to the semiconductor component, application of at least one contact/mounting element made of semiconductor material and/or metal and/or insulator material to the sold... | 01/29/2008 |
| 7323350 | Method of fabricating thin film calibration features for electron/ion beam image based metrology A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film la... | 01/29/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7325222 | Method and apparatus for verifying the post-optical proximity corrected mask wafer image sensitivity to reticle manufacturing errors A method for verifying reticle enhancement technique latent image sensitivity to mask manufacturing errors. The method includes the steps of revising a polygon based on mask CD distributions to provide a virtual mask, imaging the virtual mask to obtain response func... | 01/29/2008 |
| 7323418 | Etch-back process for capping a polymer memory device The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present ... | 01/29/2008 |
| 7322507 | Transducer assembly, capillary and wire bonding method using the same A transducer assembly and wire bonding method has a vibration unit for generating an ultrasonic wave. A body section is coupled to the vibration unit for transferring the ultrasonic wave. A tapered horn is coupled to the body section for transferring and concentrati... | 01/29/2008 |
| 7321722 | Method for thermal processing a semiconductor wafer A method for thermal processing a semiconductor wafer is disclosed. A rapid thermal processing (RTP) chamber encompasses a heating means, a rotation means, and a cooling system for cooling walls of said RTP chamber. A semiconductor wafer is loaded into the RTP chamb... | 01/22/2008 |
| 7321993 | Method and apparatus for fault detection classification of multiple tools based upon external data The present invention is generally directed to various methods and systems for fault detection control of multiple tools based upon external data. In one illustrative embodiment, the method includes monitoring each of a plurality of tools to determine if a fault con... | 01/22/2008 |
| 7320896 | Infrared radiation detector Electronic devices are disclosed that may be used for infrared radiation detection. An example electronic device includes a substrate, a transistor included in the substrate and a silicon-germanium (Si—Ge) structural layer coupled with the transistor. The structur... | 01/22/2008 |
| 7320734 | Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceil... | 01/22/2008 |
| 7319061 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 01/15/2008 |
| 7319340 | Integrated circuit load board and method having on-board test circuit An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated... | 01/15/2008 |
| 7319530 | System and method for measuring germanium concentration for manufacturing control of BiCMOS films A system and method is disclosed for measuring a germanium concentration in a semiconductor wafer for manufacturing control of BiCMOS films. Germanium is deposited over a silicon substrate layer to form a silicon germanium film. Then a rapid thermal oxidation (RTO) ... | 01/15/2008 |
| 7319942 | Molecular contaminant film modeling tool A system and method for modeling the effect of a molecular contaminant film on performance of an optical system is disclosed. A mass of material outgassed from materials of the optical system is correlated to spectrum of outgassed products. The spectrum of outgassed... | 01/15/2008 |
| 7319043 | Method and system of trace pull test The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer al... | 01/15/2008 |
| 7316872 | Etching bias reduction A patterning device for implementing a pattern on a substrate includes a main pattern feature and a sacrificial pattern feature. Both the main pattern feature and the sacrificial pattern feature are transferable to an overlying layer on the substrate. The sacrificia... | 01/08/2008 |
| 7318206 | Offset determination for measurement system matching Dynamic offset determination for each of a plurality of measurement systems for matching the systems is disclosed. One embodiment uses an artifact which is periodically run across the measurement system to be matched. Inputs for each run include the current offsets ... | 01/08/2008 |
| 7317203 | Method and monitor structure for detecting and locating IC wiring defects A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; car... | 01/08/2008 |
