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| Number | Title | Issue Date |
| 7294516 | Test patterns and methods of controlling CMP process using the same A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern regio... | 11/13/2007 |
| 7294928 | Components, methods and assemblies for stacked packages A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly e... | 11/13/2007 |
| 7294563 | Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conform... | 11/13/2007 |
| 7295291 | Apparatus and process for the determination of static lens field curvature A process for the determination of focal plane deviation uniquely due to the lens field curvature associated with a photolithographic projection tool is described. A series of lithographic exposures is performed on a resist coated silicon wafer using a stepper or sc... | 11/13/2007 |
| 7295954 | Expert knowledge methods and systems for data analysis A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one... | 11/13/2007 |
| 7295314 | Metrology/inspection positioning system A metrology/inspection system moves the imaging and/or measuring equipment of the system relative to a wafer. Accordingly, measurement or inspection of the wafer does not require that the wafer be mounted on a precision stage. This allows the wafer to be at rest on ... | 11/13/2007 |
| RE39913 | Method to control gate CD The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. U... | 11/06/2007 |
| 7291545 | Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking... | 11/06/2007 |
| 7291931 | Semiconductor device, semiconductor substrate and fabrication process of a semiconductor device A semiconductor device includes a first insulation layer including a first conductor pattern, a second insulation layer formed on the first insulation layer and including a second conductor pattern, and a third conductor pattern formed on the second insulation layer... | 11/06/2007 |
| 7291360 | Chemical vapor deposition plasma process using plural ion shower grids A chemical vapor deposition process is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower process region, each of the ion shower grids having plural orifices in mu... | 11/06/2007 |
| 7291285 | Method and system for line-dimension control of an etch process A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the ... | 11/06/2007 |
| 7291507 | Using a time invariant statistical process variable of a semiconductor chip as the chip identifier A method for providing an identifier for a semiconductor chip after the manufacture of the semiconductor chip using a fabrication process includes selecting one or more circuit elements formed on the semiconductor chip where each of the circuit elements having an el... | 11/06/2007 |
| 7288835 | Integrated circuit package-in-package system An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first inte... | 10/30/2007 |
| 7288424 | Integrated driver process flow An integrated device includes one or more device drivers and a micro-electro-mechanical system (MEMS) structure monolithically coupled to the one or more device drivers. The one or more device drivers are configured to process received control signals and to transmi... | 10/30/2007 |
| 7289214 | System and method for measuring overlay alignment using diffraction gratings A system and method for optical offset measurement is provided. An offset between two grating layers in a compound grating is measured by illuminating the gratings with light having a plane of incidence that is neither parallel with nor perpendicular to the grating ... | 10/30/2007 |
| 7288491 | Plasma immersion ion implantation process One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning... | 10/30/2007 |
| 7289215 | Image control in a metrology/inspection positioning system A metrology system includes a positioning system that produces linear and rotational motion between an imaging system and the wafer. The imaging system produces signals representing the image of the wafer in the field of view of the imaging system. A control system ... | 10/30/2007 |
| 7289230 | Wireless substrate-like sensor A wireless substrate-like sensor is provided to facilitate alignment and calibration of semiconductor processing systems. The wireless substrate-like sensor includes an optical image acquisition system that acquires one or more images of targets placed within the se... | 10/30/2007 |
| 7289864 | Feature dimension deviation correction system, method and program product A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whethe... | 10/30/2007 |
| 7287322 | Lithographic contact elements A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a... | 10/30/2007 |
| 7288206 | High-purity alkali etching solution for silicon wafers and use thereof A high-purity alkali etching solution for silicon wafers results in silicon wafers with extremely low metal impurity contamination, and excellent surface flatness. The alkali etching solution contains sodium hydroxide containing 1 ppb or less of the elements Cu, Ni,... | 10/30/2007 |
| 7284690 | Article to be processed having ID, and production method thereof A processed article is provided with a plurality of IDs having the same information for machine reading but difference to be confirmed visually. The information such as the production lot number which is read from the plurality of IDs by the reading device is the sa... | 10/23/2007 |
| 7285451 | Semiconductor integrated circuit device manufacturing method To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 | 10/23/2007 |
| 7285430 | Connection device and test system To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film ... | 10/23/2007 |
| 7282378 | Method of manufacturing inspection unit A conductive member having a first face adapted to be mounted on a board on which an inspection circuit is arranged, and a second face adapted to be opposed to a device to be inspected is prepared. The conductive member is formed with a first through hole having a f... | 10/16/2007 |
| 7282416 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 10/16/2007 |
| 7282421 | Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolation CMP process and for forming a device isolation film of a semiconductor device A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at a... | 10/16/2007 |
| 7282422 | Overlay key, method of manufacturing the same and method of measuring an overlay degree using the same An overlay key includes a first overlay key having a first main overlay pattern and a first auxiliary pattern, and a second overlay key having a second main overlay pattern and a second auxiliary overlay pattern, the second auxiliary overlay pattern formed at a loca... | 10/16/2007 |
| 7282936 | Die design with integrated assembly aid An upper die portion (36) of a die head for aligning probe pins (14) in first array of first micro-holes (18) formed in lower die portion (12) of the die head, which generally includes a spacer portion (38), a support frame (40 | 10/16/2007 |
| 7283882 | Automatic recipe validation Automated comparison of tool recipes is described. A target recipe is digitally translated from a tool language to a standard language format to produce a translated recipe. The translated recipe is digitally compared to a source recipe that is also in the standard ... | 10/16/2007 |
| 7283660 | Multi-layer printed circuit board fabrication system and method A method for aligning an image to be recorded by a direct image scanner on an upper layer of a printed circuit board with an image recorded on a lower layer thereof, the method comprising: visually imaging a portion of the image on... | 10/16/2007 |
| 7284169 | System and method for testing write strobe timing margins in memory devices Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a tra... | 10/16/2007 |
| 7283226 | Measurement system cluster Systems and methods are disclosed for measuring semiconductor wafers in a fabrication process using one or more of a plurality of measurement systems. A measurement system cluster is provided having a plurality of such measurement systems, along with a system for tr... | 10/16/2007 |
| 7283659 | Apparatus and methods for searching through and analyzing defect images and wafer maps Disclosed are methods and apparatus for automatically organizing and/or analyzing a plurality of defect images without first providing a predefined set of classified images (herein referred to as a training set). In other words, sorting is not based on a training se... | 10/16/2007 |
| 7281869 | Coating and developing system and coating and developing method A coating and developing system includes a resist film forming unit block and antireflection film forming unit blocks stacked up in layers to form a resist film and an antireflection film underlying the resist film and an antireflection film overlying the resist fil... | 10/16/2007 |
| 7282942 | Enhanced sampling methodology for semiconductor processing The present invention improves wafer sampling methods by partitioning a semiconductor wafer into a set of sampling regions and calculating yield of a sampling region(s) of the semiconductor wafer. ... | 10/16/2007 |
| 7283237 | Overlay targets with isolated, critical-dimension features and apparatus to measure overlay An optical metrology system is disclosed which is configured to minimize the measurement of specularly reflected light and measure primarily scattered light. The system is similar to prior art beam profile measurements but includes a movable baffle to selectively bl... | 10/16/2007 |
| 7283255 | Wireless substrate-like sensor A wireless substrate-like sensor is provided to facilitate alignment and calibration of semiconductor processing systems. The wireless substrate-like sensor includes an optical image acquisition system that acquires one or more images of targets placed within the se... | 10/16/2007 |
| 7282375 | Wafer level package design that facilitates trimming and testing A wafer level method of packaging, trimming and testing integrated circuits is described. A wafer having trim pads is bumped before the wafer is trimmed. After the bumping, the dice on the wafer are trimmed and tested using standard trim probing and test probing tec... | 10/16/2007 |
| 7282374 | Method and apparatus for comparing device and non-device structures The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at... | 10/16/2007 |
