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| Number | Title | Issue Date |
| 8178364 | Testing method of surface-emitting laser device and testing device thereof A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being el... | 05/15/2012 |
| 8178366 | Pattern forming method, manufacturing method of semiconductor device, and template manufacturing method In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus... | 05/15/2012 |
| 8178365 | Method of manufacturing semiconductor device A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of ... | 05/15/2012 |
| 8174283 | Calibration technique for measuring gate resistance of power MOS gate device at wafer level This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a ... | 05/08/2012 |
| 8173448 | Wafer with scribe lanes comprising external pads and/or active circuits for die testing A wafer comprises i) at least one independent die having internal integrated components, a multiplicity of internal pads connected to some of the internal integrated components, ii) scribe lanes defined between and around each independent die, and in part of which a... | 05/08/2012 |
| 8173451 | Etch stage measurement system Provided is a system for measuring an etch stage of an etch process involving one or more layers in a substrate, the etch stage measurement system configured to meet two or more etch stage measurement objectives. The system includes an etch process tool, the etch pr... | 05/08/2012 |
| 8173450 | Method of designing an etch stage measurement system Provided is a method for designing an etch stage measurement system involving an etch process for one or more layers on a substrate using an etch process tool. The etch process tool uses two or more metrology devices, at least one etch process sensor device, and a m... | 05/08/2012 |
| 8173449 | Method for making COP evaluation on single-crystal silicon wafer An evaluation area of an evaluation object wafer is concentrically divided in a radial direction, an upper limit value to the number of COPs is set in each divided evaluation segment, and an acceptance determination of the single-crystal silicon wafer is made using ... | 05/08/2012 |
| 8168450 | Semiconductor package, stacked semiconductor package having the same, and a method for selecting one semiconductor chip in a stacked semiconductor package A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A se... | 05/01/2012 |
| 8163573 | Method for manufacturing nitride semiconductor element InyGa1-yN (0 | 04/24/2012 |
| 8163572 | Method for evaluating impurity distribution under gate electrode without damaging silicon substrate A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on ... | 04/24/2012 |
| 8159257 | Element substrate, inspecting method, and manufacturing method of semiconductor device A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an... | 04/17/2012 |
| 8153451 | System and method for performing semiconductor processing on target substrate A semiconductor process system (10) includes a measuring section (40), an information processing section (51), and a control section (52). The measuring section (40) measures a characteristic of a test target film formed on a targe... | 04/10/2012 |
| 8143076 | Manufacture of defect cards for semiconductor dies A method for producing a defect card for individual dies located on a wafer, comprising: producing first and second defect cards, where the defective individual dies whose adjoining individual dies form an environment having a defect density up to a first value (δ | 03/27/2012 |
| 8134382 | Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arrang... | 03/13/2012 |
| 8124427 | Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plural... | 02/28/2012 |
| 8124428 | Structure and method for testing MEMS devices A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. Th... | 02/28/2012 |
| 8122394 | Performance-aware logic operations for generating masks A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a seco... | 02/21/2012 |
| 8119426 | Method of manufacturing an ultrasonic transducer semiconductor device A manufacturing yield of a semiconductor device (capacitive micromachined ultrasonic transducer) is increased. A plurality of first chips 1 in which a plurality of cells each having functions of transmitting and receiving ultrasonic waves are formed on a fron... | 02/21/2012 |
| 8114686 | Phase change material based temperature sensor A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads eit... | 02/14/2012 |
| 8110414 | Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the... | 02/07/2012 |
| 8093073 | Manufacturing method of a tray, a socket for inspection, and a semiconductor device The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side ... | 01/10/2012 |
| 8093072 | Substrate processing apparatus and method of manufacturing semiconductor device Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device, in which shape variations of discharge electrodes can be early detected so as to prevent a film having a non-uniform thickness from being formed on a substrate. The s... | 01/10/2012 |
| 8084277 | Semiconductor device and manufacturing method thereof A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of th... | 12/27/2011 |
| 8084278 | Method of manufacturing silicon carbide semiconductor device A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature i... | 12/27/2011 |
| 8063656 | Method of enabling a circuit board analysis A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit boar... | 11/22/2011 |
| 8062910 | Measurement of a sample using multiple models A sample that is processed to remove a top layer, e.g., using chemical mechanical polishing or etching, is accurately measured using multiple models of the sample. The multiple models may be constrained based on a pre-processing measurement of the sample. By way of ... | 11/22/2011 |
| 8053256 | Variable thickness single mask etch process The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semicon... | 11/08/2011 |
| 8053255 | STRAM with compensation element and method of making the same Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write c... | 11/08/2011 |
| 8048688 | Method and apparatus for evaluation and improvement of mechanical and thermal properties of CNT/CNF arrays A method and apparatus for the evaluation and improvement of the mechanical and thermal properties of carbon-nanotube (CNT) and carbon nanofiber (CNF) arrays grown on a substrate is disclosed. The Young's modulus of a CNT/CNF material is measured by applying an axia... | 11/01/2011 |
| 8051392 | Performance-aware logic operations for generating masks A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a seco... | 11/01/2011 |
| 8048689 | Semiconductor chip with backside conductor structure Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device... | 11/01/2011 |
| 8034640 | Apparatus and method to inspect defect of semiconductor device An apparatus and method to inspect a defect of a semiconductor device. The amount of secondary electrons generated due to a scanning electron microscope (SEM) may depend on the topology of a pattern of a semiconductor substrate. The amount of secondary electrons emi... | 10/11/2011 |
| 8026113 | Method of monitoring a semiconductor processing system using a wireless sensor network A method and system for non-invasive sensing and monitoring of a processing system employed in semiconductor manufacturing. The method allows for detecting and diagnosing drift and failures in the processing system and taking the appropriate correcting measures. The... | 09/27/2011 |
| 8021898 | Method and apparatus for controlled thermal processing A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal m... | 09/20/2011 |
| 8017411 | Dynamic adaptive sampling rate for model prediction A method and an apparatus for dynamically adjusting a sampling rate relating to wafer examination. A process step is performed upon a plurality of workpieces associated with a lot. A sample rate for acquiring metrology data relating to at least one of the processed ... | 09/13/2011 |
| 7989230 | Method for PMOS device processing using a polysilicon footing characteristic to achieve low leakage A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is chara... | 08/02/2011 |
| 7989228 | Method and structure for sample preparation for scanning electron microscopes in integrated circuit manufacturing A method for using a calibration standard. The method includes providing a calibration standard. In a specific embodiment, the calibration standard has a substrate, a thickness of material having an edge region; and a conformal material of uniform thickness disposed... | 08/02/2011 |
| 7989229 | Tactile surface inspection during device fabrication or assembly Processes for inspecting a surface during device fabrication include contacting the surface with a tactile sensor. The tactile sensor is an electroluminescent tactile sensor array or a current electrode sensor array or a capacitive sensor array. The sensor is config... | 08/02/2011 |
| 7972874 | Semiconductor process evaluation methods including variable ion implanting conditions Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under ... | 07/05/2011 |
