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| Number | Title | Issue Date |
| 8119459 | Recessed channel negative differential resistance-based memory cell Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around t... | 02/21/2012 |
| 7977165 | Method of manufacturing a semiconductor device Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the ... | 07/12/2011 |
| 7892896 | Semiconductor device having bulb-shaped recess gate and method for fabricating the same A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other to a certain distance in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plu... | 02/22/2011 |
| 7820494 | Forming of the periphery of a schottky diode with MOS trenches A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a seco... | 10/26/2010 |
| 7569431 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered wit... | 08/04/2009 |
| 7507608 | IGBT with amorphous silicon transparent collector The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom ... | 03/24/2009 |
| 7482205 | Process for resurf diffusion for high voltage MOSFET A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusio... | 01/27/2009 |
| 7452756 | Semiconductor device and manufacturing process thereof The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the... | 11/18/2008 |
| 7435628 | Method of forming a vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 10/14/2008 |
| 7374990 | Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and alig... | 05/20/2008 |
| 7368353 | Trench power MOSFET with reduced gate resistance A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof. ... | 05/06/2008 |
| 7364971 | Method for manufacturing semiconductor device having super junction construction A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is ... | 04/29/2008 |
| 7364994 | Method for manufacturing a superjunction device with wide mesas A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewal... | 04/29/2008 |
| 7358566 | Semiconductor device A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semi... | 04/15/2008 |
| 7357653 | Dual-slot memory card adapter A dual-slot memory card adapter includes a base, a space in the base, a partitioning member integrated with the adapter or separately and laterally disposed in the space to divide the space into upper and lower slot areas, one corresponding attachment each provided ... | 04/15/2008 |
| 7355223 | Vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 04/08/2008 |
| 7352036 | Semiconductor power device having a top-side drain using a sinker trench A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extend... | 04/01/2008 |
| 7351614 | Deep trench isolation for thyristor-based semiconductor device A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one ... | 04/01/2008 |
| 7332749 | Junction-gate type static induction thyristor and high-voltage pulse generator using such junction-gate type static induction thyristor A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thickne... | 02/19/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7326996 | Semiconductor device and manufacturing process thereof The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the... | 02/05/2008 |
| 7323402 | Trench Schottky barrier diode with differential oxide thickness A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination... | 01/29/2008 |
| 7323731 | Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite ... | 01/29/2008 |
| 7320895 | Thyristor-based device having dual control ports Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based se... | 01/22/2008 |
| 7314801 | Semiconductor device having a surface conducting channel and method of forming A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a met... | 01/01/2008 |
| 7312109 | Methods for fabricating fuse programmable three dimensional integrated circuits A method of fabricating a field programmable integrated circuit comprised of: constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and attaching said semiconductor device in a detachable lid pa... | 12/25/2007 |
| 7304347 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial l... | 12/04/2007 |
| 7304356 | IGBT or like semiconductor device of high voltage-withstanding capability A multiple-cell insulated-gate-bipolar-transistor chip is disclosed which includes a semiconductor substrate having formed therein a p+-type collector region and an n−-type base region, with a pn junction therebetween. An annular trench is et... | 12/04/2007 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7279397 | Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively p... | 10/09/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7279408 | Semiconductor device, method for manufacturing the same, and plating solution The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surfac... | 10/09/2007 |
| 7279368 | Method of manufacturing a vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 10/09/2007 |
| 7279725 | Vertical diode structures A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interio... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7276762 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 10/02/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7276405 | Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semicondu... | 10/02/2007 |
| 7273771 | Common MOSFET process for plural devices A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusio... | 09/25/2007 |
