Class 438/136 - Junction gate

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a regenerative switching device which
No. of patents: 23
Last issue date: 02/10/2009

Number	Title	Issue Date
7488627	Thyristor-based memory and its method of operation A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of...	02/10/2009
7351614	Deep trench isolation for thyristor-based semiconductor device A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one ...	04/01/2008
7332749	Junction-gate type static induction thyristor and high-voltage pulse generator using such junction-gate type static induction thyristor A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thickne...	02/19/2008
7314801	Semiconductor device having a surface conducting channel and method of forming A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a met...	01/01/2008
7288786	Integrated circuit configuration with analysis protection and method for producing the configuration During the creation of wiring plans for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects serve to protect the integrated circuit....	10/30/2007
7242040	Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,...	07/10/2007
7115471	Method of manufacturing semiconductor device including nonvolatile memory There is provided a method of manufacturing a semiconductor device including a nonvolatile memory including forming an element isolation area surrounding an element area in a semiconductor substrate doped with a first type conductive impurity, forming a gate insulat...	10/03/2006
7045397	JFET and MESFET structures for low voltage high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th...	05/16/2006
7005678	Silicon carbide semiconductor device having junction field effect transistor and method for manufacturing the same A silicon carbide semiconductor device includes: a semiconductor substrate including a base substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are laminated in this order; a cell portion disposed in the semico...	02/28/2006
6995052	Method and structure for double dose gate in a JFET A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed af...	02/07/2006
6995424	Non-volatile memory devices with charge storage insulators A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the ce...	02/07/2006
6921932	JFET and MESFET structures for low voltage, high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th...	07/26/2005
6919241	Superjunction device and process for its manufacture A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward ...	07/19/2005
6812070	Epitaxially-grown backward diode A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n juncti...	11/02/2004
6780684	Stabilized tunnel junction component A method for stabilizing a tunnel junction component, in which a mask is formed on the surface of a substrate, and conductors are constructed by evaporation onto the substrate in an evaporation chamber, and at least one thin oxide layer element is oxidized on top of...	08/24/2004
6773968	High density planar SRAM cell using bipolar latch-up and gated diode breakdown Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided a...	08/10/2004
6762080	Method of manufacturing a semiconductor device having a cathode and an anode from a wafer In a method of manufacturing a semiconductor element (6) having a cathode (3) and an anode (5), the starting material used is a relatively thick wafer (1) to which, as a first step, a barrier region (21) is added on the anode side....	07/13/2004
6306690	Process flow to integrate high and low voltage peripheral transistors with a floating gate array The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a fl...	10/23/2001
5956577	Method of manufacturing serrated gate-type or joined structure A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to ...	09/21/1999
5851855	Process for manufacturing a MOS-technology power device chip and package assembly A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functiona...	12/22/1998
5702962	Fabrication process for a static induction transistor A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N-...	12/30/1997
5411901	Method of making high voltage transistor In a method for constructing a semiconducting device, within a substrate of a first conductivity type there is formed a well of second conductivity type. Within the well, an extended drain region of a first conductivity type is formed. An insulating regio...	05/02/1995
3986904	Process for fabricating planar SCR structure A low resistivity anode region is formed relative to the much higher resistivity gate region in a planar semiconductor controlled rectifier (SCR) structure. The low resistivity anode region is achieved by diffusing an appropriate impurity in high concentr...	10/19/1976

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Class 438/136 - Junction gate