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| Number | Title | Issue Date |
| 8048724 | Semiconductor switching device A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar t... | 11/01/2011 |
| 8048723 | Germanium FinFETs having dielectric punch-through stoppers A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to... | 11/01/2011 |
| 7919364 | Semiconductor devices and methods of manufacture thereof A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the... | 04/05/2011 |
| 7897440 | Vertical thyristor-based memory with trench isolation and method of fabrication thereof A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first di... | 03/01/2011 |
| 7883941 | Methods for fabricating memory cells and memory devices incorporating the same A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a secon... | 02/08/2011 |
| 7842558 | Masking process for simultaneously patterning separate regions According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a sec... | 11/30/2010 |
| 7824968 | LDMOS using a combination of enhanced dielectric stress layer and dummy gates First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Secon... | 11/02/2010 |
| 7638370 | Method for producing multi-gate field-effect transistor with fin structure having drain-extended MOS field-effect transistor In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at l... | 12/29/2009 |
| 7534665 | Method of manufacturing semiconductor device In a semiconductor device manufacturing method of the present invention, a polysilicon film and a silicon nitride film are deposited on an upper surface of an epitaxial layer. Patterning is performed so that the polysilicon film and the silicon nitride film are left... | 05/19/2009 |
| 7504286 | Semiconductor memory devices and methods for fabricating the same A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well ... | 03/17/2009 |
| 7456054 | Gated lateral thyristor-based random access memory cell (GLTRAM) One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated,... | 11/25/2008 |
| 7439102 | Semiconductor fuse box and method for fabricating the same A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include ... | 10/21/2008 |
| 7408190 | Thin film transistor and method of forming the same A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer i... | 08/05/2008 |
| 7372105 | Semiconductor device with power supply impurity region A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing... | 05/13/2008 |
| 7368761 | Electrostatic discharge protection device and fabrication method thereof An electrostatic discharge (ESD) protection device and a fabrication method thereof are provided. The ESD protection device with an embedded high-voltage P type SCR (EHVPSCR) structure of the present invention is employed to guide the ESD current/voltage to a system... | 05/06/2008 |
| 7364971 | Method for manufacturing semiconductor device having super junction construction A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is ... | 04/29/2008 |
| 7361555 | Trench-gate transistors and their manufacture A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick ... | 04/22/2008 |
| 7359169 | Circuit for protecting integrated circuits against electrostatic discharges A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply volta... | 04/15/2008 |
| 7351614 | Deep trench isolation for thyristor-based semiconductor device A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one ... | 04/01/2008 |
| 7341902 | Finfet/trigate stress-memorization method Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the sem... | 03/11/2008 |
| 7323375 | Fin field effect transistor device and method of fabricating the same Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped ... | 01/29/2008 |
| 7301203 | Superjunction semiconductor device In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the ... | 11/27/2007 |
| 7291887 | Protection circuit for electrostatic discharge A protection circuit protects an integrated circuit (“IC”) from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the ... | 11/06/2007 |
| 7285456 | Method of fabricating a fin field effect transistor having a plurality of protruding channels In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate havin... | 10/23/2007 |
| 7285805 | Low reference voltage ESD protection device In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS. ... | 10/23/2007 |
| 7285458 | Method for forming an ESD protection circuit An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output ... | 10/23/2007 |
| 7279367 | Method of manufacturing a thyristor semiconductor device In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-bl... | 10/09/2007 |
| 7273771 | Common MOSFET process for plural devices A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusio... | 09/25/2007 |
| 7274047 | Silicon controlled rectifier electrostatic discharge protection device for power supply lines with powerdown mode of operation An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first r... | 09/25/2007 |
| 7271040 | Electrode contact section of semiconductor device A p-type impurity layer is formed in an n-type semiconductor substrate. Since the p-type impurity layer has a low impurity concentration and a sufficiently shallow depth of 1.0 μm or less, the carrier injection coefficient can be reduced. In the p-type impurity lay... | 09/18/2007 |
| 7268079 | Method for fabricating a semiconductor having a field zone A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in... | 09/11/2007 |
| 7253030 | Method of fabricating high-voltage CMOS device The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown ... | 08/07/2007 |
| 7250327 | Silicon die substrate manufacturing process and silicon die substrate with integrated cooling mechanism In one embodiment a method is provided. The method comprises inserting a first end of a P-type semiconductor pin in a first through hole via in a substrate; inserting a first end of an N-type semiconductor pin in a second through hole via in the substrate; and elect... | 07/31/2007 |
| 7245466 | Pumped SCR for ESD protection An ESD protection device can include a silicon-controlled rectifier (SCR) and an external pumping circuit. The external pumping circuit can be used to forward bias a junction of the SCR. The external pumping circuit can comprise a transistor that can be coupled to a... | 07/17/2007 |
| 7242040 | Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,... | 07/10/2007 |
| 7224002 | Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor formed entirely in the floating substrate, an... | 05/29/2007 |
| 7215004 | Integrated circuit device with electronically accessible device identifier An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to int... | 05/08/2007 |
| 7211200 | Manufacture and cleaning of a semiconductor Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etc... | 05/01/2007 |
| 7202528 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power... | 04/10/2007 |
| 7186594 | High voltage ESD-protection structure A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a vol... | 03/06/2007 |
