Class 438/131 - Using structure alterable to conductive state (i.e., antifuse)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making an array of electrical devices and selectively
No. of patents: 296
Last issue date: 04/03/2012

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Number	Title	Issue Date
8148211	Semiconductor structure processing using multiple laser beam spots spaced on-axis delivered simultaneously Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates ...	04/03/2012
7981731	Method of forming a high impedance antifuse A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a ...	07/19/2011
7919363	Integrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereof A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions wi...	04/05/2011
7915095	Silicide-silicon oxide-semiconductor antifuse device and method of making An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. ...	03/29/2011
7915093	System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The ...	03/29/2011
7915094	Method of making a diode read/write memory cell in a programmed state A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrical...	03/29/2011
7846782	Diode array and method of making thereof A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semicondu...	12/07/2010
7833843	Method for forming a memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide A method of forming a memory cell involves forming a semiconductor junction diode in series with an antifuse. The cell is programmed by rupture of the antifuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. ...	11/16/2010
7820492	Electrical fuse with metal silicide pipe under gate electrode An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal s...	10/26/2010
7816189	Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ...	10/19/2010
7816188	Process for fabricating a dielectric film using plasma oxidation A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer havin...	10/19/2010
7790518	Method of trimming semiconductor elements with electrical resistance feedback A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through th...	09/07/2010
7790517	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device forms an N− diffusion layer to be a source/drain region of a grooved transistor simultaneously with an N− diffusion layer of a channel region directly under a gate electrode of an antifuse el...	09/07/2010
7700415	Stacked bit line dual word line nonvolatile memory An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word line...	04/20/2010
7691684	Fin-type antifuse A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting t...	04/06/2010
7678620	Antifuse one time programmable memory array and method of manufacture A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plura...	03/16/2010
7655509	Silicide-silicon oxide-semiconductor antifuse device and method of making An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. ...	02/02/2010
7651892	Electrical programmable metal resistor The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semicondu...	01/26/2010
7642138	Split-channel antifuse array architecture An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a proce...	01/05/2010
7618850	Method of making a diode read/write memory cell in a programmed state A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrical...	11/17/2009
7601564	Semiconductor device including memory cell and anti-fuse element A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in t...	10/13/2009
7585704	Method of producing highly strained PECVD silicon nitride thin films at low temperature A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface o...	09/08/2009
7572682	Semiconductor structure for fuse and anti-fuse applications A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and t...	08/11/2009
7569429	Antifuse having uniform dielectric thickness and method for fabricating the same Disclosed are an antifuse having a uniform amorphous silicon (antifuse material) thickness and a method for fabricating such an antifuse device. The antifuse is located between overlying and underlying conductive layers, and includes: a contact and/or via hole in an...	08/04/2009
7553704	Antifuse element and method of manufacture An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having a...	06/30/2009
7537968	Junction diode with reduced reverse current A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at lea...	05/26/2009
7528015	Tunable antifuse element and method of manufacture A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a po...	05/05/2009
7507607	Method of forming a silicide bridged anti-fuse with a tungsten plug metalization process A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an el...	03/24/2009
7488625	Vertically stacked, field programmable, nonvolatile memory and method of fabrication A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fu...	02/10/2009
7442626	Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac...	10/28/2008
7439102	Semiconductor fuse box and method for fabricating the same A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include ...	10/21/2008
7420242	Stacked bit line dual word line nonvolatile memory An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word line...	09/02/2008
7410838	Fabrication methods for memory cells A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer a...	08/12/2008
7405420	Method and system for chalcogenide-based nanowire memory Chalcogenide-based nanowire memories are implemented using a variety of methods and devices. According to an example embodiment of the present invention, a method of manufacturing a memory circuit is implemented. The method includes depositing nanoparticles at locat...	07/29/2008
7402463	Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure compri...	07/22/2008
7402888	Input protection circuit preventing electrostatic discharge damage of semiconductor integrated circuit An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which ...	07/22/2008
7402855	Split-channel antifuse array architecture Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technolo...	07/22/2008
7393722	Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer sel...	07/01/2008
7393721	Semiconductor chip with metallization levels, and a method for formation in interconnect structures A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in ...	07/01/2008
7368801	Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon la...	05/06/2008

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Class 438/131 - Using structure alterable to conductive state (i.e., antifuse)